Dilip P. Vasudevan

26 papers B 1C 3Journal 6Unranked 16

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Language Support for Navigating Architecture Design in Closed Form. ACM J. Emerg. Technol. Comput. Syst. Weilong Cui, Georgios Tzimpragos, Yu Tao, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan, Timothy Sherwood
2019	—	`conf`	3D photonics as enabling technology for deep 3D DRAM stacking. MEMSYS Sebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan
2019	B	`conf`	PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. ISPASS Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf
2017	—	`conf`	CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. NANOARCH Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf
2017	—	`conf`	Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. ISC Workshops Dilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf
2015	J	`jnl`	10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. SIGARCH Comput. Archit. News Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati
2015	J	`jnl`	A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems. IEEE Trans. Biomed. Circuits Syst. Abhishek Roy, Alicia Klinefelter, Farah B. Yahya, Xing Chen, Luisa Patricia Gonzalez-Guerrero, Christopher J. Lukas, Divya Akella Kamakshi, James Boley, Kyle Craig, Muhammad Faisal, Seunghyun Oh, Nathan E. Roberts, Yousef Shakhsheer, Aatmesh Shrivastava, Dilip P. Vasudevan, David D. Wentzloff, Benton H. Calhoun
2015	—	`conf`	The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data. ACM Great Lakes Symposium on VLSI Dilip P. Vasudevan, Andrew A. Chien
2012	J	`jnl`	Ultra Low Power Asynchronous Charge Sharing Logic. J. Low Power Electron. Jiaoyan Chen, Dilip P. Vasudevan, Michel P. Schellekens, Emanuel M. Popovici
2012	—	`conf`	Ultra Low Power Booth Multiplier Using Asynchronous Logic. ASYNC Jiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens
2011	C	`conf`	Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. DSD Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens
2011	—	`conf`	Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing. 3DIC Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee
2010	—	`conf`	Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations. ICECS Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen
2010	—	`conf`	Reversible online BIST using bidirectional BILBO. Conf. Computing Frontiers Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens
2010	C	`conf`	Static Average Case Power Estimation Technique for Block Ciphers. DSD Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens
2008	C	`conf`	A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS Dilip P. Vasudevan, Aristides Efthymiou
2007	J	`jnl`	Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2006	J	`jnl`	Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson
2006	—	`conf`	Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. DELTA Jia Di, Dilip P. Vasudevan
2005	—	`conf`	A Technique for Modular Design of Self-Checking Carry-Select Adder. DFT Dilip P. Vasudevan, Parag K. Lala
2005	—	`conf`	CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2005	—	`conf`	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT Jia Di, Parag K. Lala, Dilip P. Vasudevan
2004	—	`conf`	A New Reversible Logic Gate and its Applications. ESA/VLSI Dilip P. Vasudevan, Parag K. Lala
2004	—	`conf`	A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2004	—	`conf`	Logic implementation using a reversible gate. Circuits, Signals, and Systems Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala
2004	—	`conf`	Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson