Dilip K. Bhavsar

23 papers A* 1A 10C 1Misc 5Journal 6
YearRankTypeTitle / Venue / Authors
2011 Misc conf
Harmony Widget for X-free scan testing.
VTS
Dilip K. Bhavsar
2011 A conf
Test access and the testability features of the Poulson multi-core Intel Itanium® processor.
ITC
Dilip K. Bhavsar, Steve Poehlman
2005 Misc conf
A Built-in Self-Test Method for Write-only Content Addressable Memories.
VTS
Dilip K. Bhavsar
2003 C conf
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.
ICCD
Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies
2003 A conf
Testability Features of the Alpha 21364 Microprocessor.
ITC
Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies
2002 Misc conf
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor.
VTS
Dilip K. Bhavsar, Richard A. Davies
2001 Misc conf
Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits.
VLSI Design
Dilip K. Bhavsar, Rishan Tan
2001 Misc conf
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester.
VTS
Dilip K. Bhavsar
2000 J jnl
Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability.
IEEE Des. Test Comput.
Dilip K. Bhavsar
1999 A conf
An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264.
ITC
Dilip K. Bhavsar
1999 J jnl
ITC 99 Panels.
IEEE Des. Test Comput.
Dilip K. Bhavsar
1998 A conf
A highly testable and diagnosable fabrication process test chip.
ITC
Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill
1998 J jnl
ITC 97 Panel Sessions.
IEEE Des. Test Comput.
Dilip K. Bhavsar, Yervant Zorian
1998 A conf
Testability access of the high speed test features in the Alpha 21264 microprocessor.
ITC
Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson
1997 J jnl
Alpha 21164 Testability Strategy.
IEEE Des. Test Comput.
Dilip K. Bhavsar, John H. Edmondson
1994 A conf
Testability Strategy of the ALPHA AXP 21164 Microprocessor.
ITC
Dilip K. Bhavsar, John H. Edmondson
1991 A conf
An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes.
ITC
Dilip K. Bhavsar
1991 J jnl
Testing Interconnections to Static RAMs.
IEEE Des. Test Comput.
Dilip K. Bhavsar
1986 J jnl
A New Economical Implementation for Scannable Flip-Flops in MOS.
IEEE Des. Test
Dilip K. Bhavsar
1985 A conf
"Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test.
ITC
Dilip K. Bhavsar
1984 A conf
Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ?
ITC
Dilip K. Bhavsar, Balakrishnan Krishnamurthy
1983 A* conf
Design For Test Calculus: An algorithm for DFT rules checking.
DAC
Dilip K. Bhavsar
1981 A conf
Self-Testing by Polynomial Division.
ITC
Dilip K. Bhavsar, Richard W. Heckelman