Dilip K. Banerji

36 papers B 1C 4Misc 5Journal 16Unranked 10
YearRankTypeTitle / Venue / Authors
2011 J jnl
A hierarchical architecture for detecting selfish behaviour in community wireless mesh networks.
Comput. Commun.
Nikhil Saxena, Mieso K. Denko, Dilip K. Banerji
2009 J jnl
Meta-Heuristic Based Techniques for FPGA Placement: A Study.
Int. J. Comput. Their Appl.
Shawki Areibi, X. Bao, Gary Gréwal, Dilip K. Banerji, Peng Du
2009 — conf
Near-linear wirelength estimation for FPGA placement.
CCECE
Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji
2007 J jnl
Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic.
Appl. Intell.
Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton
2006 — conf
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times.
CCECE
Shouvik Chowdhury, Gary William Grewal, Dilip K. Banerji
2006 — conf
Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain.
Artificial Intelligence and Applications
Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton
2006 B conf
Optimized Memory Assignment for DSPs.
IEEE Congress on Evolutionary Computation
Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton, Mario Ventresca
2004 — conf
A Fast Hierarchical Approach to FPGA Placement.
ESA/VLSI
Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji
2004 Misc conf
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
VLSI Design
Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji
2003 Misc conf
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.
VLSI Design
Zhibin Dai, Dilip K. Banerji
1999 — conf
Routability Prediction for Hierarchical FPGAs.
Great Lakes Symposium on VLSI
Wei Li, Dilip K. Banerji
1996 J jnl
A Modified Approach to Test Plan Generation for Combinational Logic Blocks.
VLSI Design
Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia
1996 Misc conf
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.
VLSI Design
J. Shu, Thomas Charles Wilson, Dilip K. Banerji
1995 J jnl
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis.
VLSI Design
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
1994 C conf
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
ICCD
Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
1994 — conf
An ILP-based approach to code generation.
Code Generation for Embedded Processors
Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji
1994 — conf
An integrated approach to retargetable code generation.
HLSS
Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji
1993 Misc conf
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.
VLSI Design
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
1993 — conf
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis.
Great Lakes Symposium on VLSI
Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji
1992 Misc conf
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test.
VLSI Design
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
1991 — conf
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits.
Great Lakes Symposium on VLSI
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
1991 — conf
Test plan generation and concurrent scheduling of tests in the presence of conflicts.
Great Lakes Symposium on VLSI
Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia
1988 J jnl
A Semantic Approach for Modular Synthesis of VLSI Systems.
Inf. Process. Lett.
M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
1988 J jnl
Allocation of multiport memories in data path synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia
1988 J jnl
Synthesis of decentralised controllers from high level description.
Microprocess. Microprogramming
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
1986 J jnl
An optimal distributed solution to the dining philosophers problem.
Int. J. Parallel Program.
S. P. Rana, Dilip K. Banerji
1984 J jnl
On Combinational Logic for Sign Detection in Residue Number Systems.
Aust. Comput. J.
Dilip K. Banerji, Saroj Kaushik
1983 C conf
Representation and processing of fractions in a residue system.
IEEE Symposium on Computer Arithmetic
Dilip K. Banerji, Saroj Kaushik
1976 J jnl
Using a Microprocessor in an Intelligent Graphics Terminal.
Computer
Jacques Raymond, Dilip K. Banerji
1975 C conf
On combinational logic for sign detection in residue number systems.
IEEE Symposium on Computer Arithmetic
Dilip K. Banerji
1974 J jnl
A Novel Implementation Method for Addition and Subtraction in Residue Number Systems.
IEEE Trans. Computers
Dilip K. Banerji
1974 J jnl
On the Use of Residue Arithmetic for Computation.
IEEE Trans. Computers
Dilip K. Banerji
1973 J jnl
On Control Memory Minimization in Microprogrammed Digital Computers.
IEEE Trans. Computers
S. R. Das, Dilip K. Banerji, A. Chattopadhyay
1972 C conf
"A novel implementation method for addition and subtraction in residue number systems".
IEEE Symposium on Computer Arithmetic
Dilip K. Banerji
1972 J jnl
On Translation Algorithms in Residue Number Systems.
IEEE Trans. Computers
Dilip K. Banerji, Janusz A. Brzozowski
1969 J jnl
Sign Detection in Residue Number Systems.
IEEE Trans. Computers
Dilip K. Banerji, Janusz A. Brzozowski