Diksha Shekhawat

12 papers C 1Misc 2Journal 3Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Energy and performance efficient NAND flash translation layer architecture for low-latency edge applications.
J. Parallel Distributed Comput.
Ranjeeth Sekhar, Diksha Shekhawat, Jugal Gandhi, M. Santosh, Jai Gopal Pandey
2025 C conf
DyLock: A Dynamic Key-based SAT and Structural Attacks Resilient Low-overhead Logic Locking.
ISCAS
Jugal Gandhi, Diksha Shekhawat, Jaya Dofe, Jai Gopal Pandey
2025 Misc conf
SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation.
VLSID
Jugal Gandhi, Nikhil Handa, Abhay Nayak, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey
2024 — conf
Emerging Frontiers and Limitations of Logic Locking for Secure IC Design.
MCSoC
Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey
2024 — conf
Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design.
ATS
Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey
2024 J jnl
Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher.
J. Real Time Image Process.
Kartik Jhawar, Jugal Gandhi, Diksha Shekhawat, Aniket Upadhyay, Avadh Harkishanka, Nitin Chaturvedi, M. Santosh, Jai Gopal Pandey
2024 Misc conf
SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking.
VLSID
Jugal Gandhi, Rishi Agarwal, Anish Mall, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey
2023 — conf
LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking.
APCCAS
Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey
2023 J jnl
Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends.
Comput. Secur.
Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey
2023 — conf
PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations.
CoNGA
Diksha Shekhawat, Jugal Gandhi, M. Santosh, Jai Gopal Pandey
2023 — conf
Security Evaluation of Lightweight SBoxes.
iSES
Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey
2021 — conf
A Hardware Generator for Posit Arithmetic and its FPGA Prototyping.
VDAT
Diksha Shekhawat, Apoorva Jangir, Jai Gopal Pandey