Dietmar Fey - RankMe

218 papers A 2B 10C 17Misc 6Journal 54Unranked 120

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	CSD-Driven Speedup in RISC-V Processor. DASIP Farhad EbrahimiAzandaryani, Dietmar Fey
2025	—	`conf`	FORnanoSatellites - Innovations in Nano-satellites - A Bavarian Research Alliance. ARCS Dietmar Fey, Klaus Schilling, Jörg Franke, M. Schmidt, C. Fuchs
2025	—	`conf`	FPGA Implementation of a Real-Time Application Based on RISC-V Cores. SSD Amr Abdelhafez, Farhad EbrahimiAzandaryani, Maurizio Bianconi, Dietmar Fey
2025	—	`conf`	Multiplier-Free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic. MCSoC Felix Zeller, John Reuben, Dietmar Fey
2025	J	`jnl`	Multiplier-free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic. CoRR Felix Zeller, John Reuben, Dietmar Fey
2025	J	`jnl`	RISC-V CPU Design Using RRAM-CMOS Standard Cells. IEEE Trans. Very Large Scale Integr. Syst. Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Jianan Wen, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, Christian Wenger
2025	C	`conf`	Smart Sensing of Multi-bit Resistive Memory using a Single Reference. DSD John Reuben, Dietmar Fey
2025	—	`conf`	Specification of Generic Memristor-Based Crossbar Architectures for In-Memory Computing. MOCAST Benjamin Seiler, Dietmar Fey
2025	—	`conf`	Ternary Signed Digit Addition on Field Programmable Gate Arrays. ARCS Thomas Schlögl, Dietmar Fey
2025	—	`conf`	Using a SystemC Based Design and Simulation System for Hyperdimensional Computing with Multi-Level-Cell Look-Up-Tables with ReRAM. MetroXRAINE Benjamin Seiler, John Reuben, Dietmar Fey
2024	—	`ed.`	Architecture of Computing Systems - 37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings ARCS Dietmar Fey, Benno Stabernack, Stefan Lankes, Mathias Pacher, Thilo Pionteck
2024	—	`conf`	Area-Efficient Digital Design Using RRAM-CMOS Standard Cells. ISVLSI Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Markus Andreas Schubert, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, Christian Wenger
2024	—	`conf`	Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level. ARCS Johannes Kliemt, Markus Fritscher, Dietmar Fey
2024	J	`jnl`	ExTern: Boosting RISC-V core performance using ternary encoding. Microprocess. Microsystems Farhad Ebrahimi-Azandaryani, Dietmar Fey
2024	J	`jnl`	HyFAR: A hypervisor-based fault tolerance approach for heterogeneous automotive real-time systems. J. Syst. Archit. Johannes Lex, Ulrich Margull, Ralph Mader, Dietmar Fey
2024	—	`conf`	On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory. NorCAS John Reuben, Suzanne Lancaster, Dietmar Fey, Stefan Slesazeck
2024	C	`conf`	Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory. DSD Shima Hosseinzadeh, Suzanne Lancaster, Amirhossein Parvaresh, Cláudia Silva, Dietmar Fey
2023	—	`conf`	A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories. MOCAST John Reuben, Dietmar Fey, Stefan Slesazeck
2023	J	`jnl`	Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures. IEEE Comput. Archit. Lett. Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Dietmar Fey
2023	—	`conf`	DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs. EDGE Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Dietmar Fey
2023	—	`conf`	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions. NANOARCH Stefan Slesazeck, Suzanne Lancaster, John Reuben, Shima Hosseinzadeh, Dietmar Fey, Thomas Mikolajick
2023	J	`jnl`	Memristive computing in Germany. it Inf. Technol. Dietmar Fey
2023	—	`conf`	Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture. ARCS Shima Hosseinzadeh, Amirhossein Parvaresh, Dietmar Fey
2023	J	`jnl`	Optimizing multi-level ReRAM memory for low latency and low energy consumption. it Inf. Technol. Shima Hosseinzadeh, Marius Klemm, Georg Fischer, Dietmar Fey
2023	—	`conf`	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study. NANOARCH Amirhossein Parvaresh, Shima Hosseinzadeh, Dietmar Fey
2023	C	`conf`	Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing. SIMULTECH Johannes Kliemt, Dietmar Fey
2022	J	`jnl`	Closing the Performance Gap with Modern C++. CoRR Thomas Heller, Hartmut Kaiser, Patrick Diehl, Dietmar Fey, Marc Alexander Schweitzer
2022	—	`conf`	EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis. SAMOS Lars Schwenger, Philipp Holzinger, Dietmar Fey, Hector Gerardo Muñoz Hernandez, Marc Reichenbach
2022	—	`conf`	Investigating SAMV Regarding its Suitability For FPGAs. SOCC Farehe Giahi, Sebastian Rachuj, Dietmar Fey
2021	B	`conf`	A Case for Function-as-a-Service with Disaggregated FPGAs. CLOUD Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Marc Reichenbach, Dietmar Fey
2021	J	`jnl`	Adaptation Strategies for Personalized Gait Neuroprosthetics. Frontiers Neurorobotics Anne D. Koelewijn, Musa L. Audu, Antonio J. del Ama, Annalisa Colucci, Josep M. Font-Llagunes, Antonio Gogeascoechea, Sandra K. Hnat, Nathan S. Makowski, Juan C. Moreno, Mark J. Nandor, Roger D. Quinn, Marc Reichenbach, Ryan-David Reyes, Massimo Sartori, Surjo R. Soekadar, Ronald J. Triolo, Mareike Vermehren, Christian Wenger, Utku S. Yavuz, Dietmar Fey, Philipp Beckerle
2021	—	`conf`	Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. ISVLSI John Reuben, Dietmar Fey
2021	—	`conf`	Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic. ICECS Dietmar Fey, John Reuben, Stefan Slesazeck
2021	—	`conf`	Fault Tolerance in Heterogeneous Automotive Real-time Systems. Echtzeit Johannes Lex, Ulrich Margull, Dietmar Fey, Ralph Mader
2021	J	`jnl`	RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. IEEE Access Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey
2021	—	`conf`	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. LASCAS Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach
2021	C	`conf`	Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design. ISORC Steffen Vaas, Peter Ulbrich, Christian Eichler, Peter Wägemann, Marc Reichenbach, Dietmar Fey
2020	—	`conf`	A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. MOCAST Johannes Knödtel, Markus Fritscher, Daniel Reiser, Dietmar Fey, Marco Breiling, Marc Reichenbach
2020	J	`jnl`	Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. Supercomput. Front. Innov. Johannes Hofmann, Christie L. Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein
2020	—	`conf`	Direct state transfer in MLC based memristive ReRAM devices for ternary computing. ECCTD Dietmar Fey, John Reuben
2020	—	`conf`	Impact of Performance Estimation on Fast Processor Simulators. SimuTools (2) Sebastian Rachuj, Dietmar Fey, Marc Reichenbach
2020	J	`jnl`	Memristoren für zukünftige Rechnersysteme. Inform. Spektrum Dietmar Fey, Wolfgang Karl, Theo Ungerer
2020	—	`conf`	Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation. H2RC@SC Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
2020	C	`conf`	TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities. DSD Shima Hosseinzadeh, Mehrdad Biglari, Dietmar Fey
2020	J	`jnl`	The allscale framework architecture. Parallel Comput. Herbert Jordan, Philipp Gschwandtner, Peter Thoman, Peter Zangerl, Alexander Hirsch, Thomas Fahringer, Thomas Heller, Dietmar Fey
2020	Misc	`conf`	ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters. FCCM Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
2019	—	`conf`	A Generic Functional Simulation of Heterogeneous Systems. ARCS Sebastian Rachuj, Marc Reichenbach, Dietmar Fey
2019	—	`conf`	A Hardware Inference Accelerator for Temporal Convolutional Networks. NORCAS Rashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger, Marco Breiling, Marc Reichenbach, Dietmar Fey
2019	—	`conf`	A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. NORCAS John Reuben, Dietmar Fey
2019	J	`jnl`	Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. J. Signal Process. Syst. Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey
2019	J	`jnl`	Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. CoRR Johannes Hofmann, Christie L. Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein
2019	—	`conf`	Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing. FAS*W@SASO/ICAC Alexander Ditter, Michael Tielemann, Dietmar Fey
2019	J	`jnl`	Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. J. Signal Process. Syst. Tobias Lieske, Wilfried Uhring, Norbert Dumas, Anastasia Ioanna Skilitski, Jérémie Léonard, Dietmar Fey
2019	J	`jnl`	Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms. J. Signal Process. Syst. Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey
2019	—	`conf`	Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools. ICECS Markus Fritscher, Johannes Knödtel, Marc Reichenbach, Dietmar Fey
2019	B	`conf`	System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration. FPL Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
2018	—	`conf`	A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. ARCS Sebastian Rachuj, Christian Herglotz, Marc Reichenbach, André Kaup, Dietmar Fey
2018	—	`conf`	A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. PATMOS Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey
2018	—	`conf`	A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems. SAMOS Philipp Holzinger, Marc Reichenbach, Dietmar Fey
2018	J	`jnl`	A programmable ternary CPU using hybrid CMOS/memristor circuits. Int. J. Parallel Emergent Distributed Syst. Daniel Wust, Dietmar Fey, Johannes Knödtel
2018	J	`jnl`	An extended analysis of memory hierarchies for efficient implementations of image processing applications. J. Real Time Image Process. Christian Hartmann, Dietmar Fey
2018	—	`conf`	Autonomous Driving in the Curriculum of Computer Architecture. EWME Sebastian Rachuj, Marc Reichenbach, Steffen Vaas, Dietmar Fey
2018	J	`jnl`	Case study on memristor-based multilevel memories. Int. J. Circuit Theory Appl. Christopher Soell, Marc Reichenbach, Juergen Roeber, Amelie Hagelauer, Robert Weigel, Dietmar Fey
2018	—	`conf`	Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures. DASIP Marc Reichenbach, Lukas Liebischer, Steffen Vaas, Dietmar Fey
2018	J	`jnl`	Guest Editorial Memristive-Device-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing
2018	—	`conf`	High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. NANOARCH Mehrdad Biglari, Tobias Lieske, Dietmar Fey
2018	J	`jnl`	IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures. J. Real Time Image Process. Christian Hartmann, Konrad Häublein, Marc Reichenbach, Dietmar Fey
2018	—	`conf`	Multi-level memristive voltage divider: programming scheme trade-offs. MEMSYS Tobias Lieske, Mehrdad Biglari, Dietmar Fey
2018	C	`conf`	On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors. ISC Johannes Hofmann, Georg Hager, Dietmar Fey
2018	J	`jnl`	On the accuracy and usefulness of analytic energy models for contemporary multicore processors. CoRR Johannes Hofmann, Georg Hager, Dietmar Fey
2018	—	`conf`	Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems. Euro-Par Workshops Wolfgang Bauer, Philipp Holzinger, Marc Reichenbach, Steffen Vaas, Paul Hartke, Dietmar Fey
2018	J	`jnl`	Special issue on heterogeneous real-time image processing. J. Real Time Image Process. Dietmar Fey, Frank Hannig
2018	C	`conf`	The AllScale Runtime Application Model. CLUSTER Herbert Jordan, Thomas Heller, Philipp Gschwandtner, Peter Zangerl, Peter Thoman, Dietmar Fey, Thomas Fahringer
2018	—	`conf`	The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM. HPCS Anderson M. Maliszewski, Dalvan Griebler, Claudio Schepke, Alexander Ditter, Dietmar Fey, Luiz Gustavo Fernandes
2017	C	`conf`	An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. ISC Johannes Hofmann, Georg Hager, Gerhard Wellein, Dietmar Fey
2017	J	`jnl`	An analysis of core- and chip-level architectural features in four generations of Intel server processors. CoRR Johannes Hofmann, Georg Hager, Gerhard Wellein, Dietmar Fey
2017	J	`jnl`	Comparison of common parallel architectures for the execution of the island model and the global parallelization of evolutionary algorithms. Concurr. Comput. Pract. Exp. Steffen Limmer, Dietmar Fey
2017	J	`jnl`	Comprehensive curriculum for reconfigurable heterogeneous computer architecture education. IET Circuits Devices Syst. Benjamin Pfundt, Marc Reichenbach, Dietmar Fey
2017	—	`conf`	Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics. DASIP Tobias Lieske, Wilfried Uhring, Norbert Dumas, Jérémie Léonard, Dietmar Fey
2017	J	`jnl`	Evaluating Ternary Adders using a hybrid Memristor / CMOS approach. CoRR Dietmar Fey
2017	J	`jnl`	Fast heterogeneous computing architectures for smart antennas. J. Syst. Archit. Marc Reichenbach, Maximilian Kasparek, Konrad Häublein, Jan Niklas Bauer, Mohammad Alawieh, Dietmar Fey
2017	—	`conf`	Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure. CCB@EuroSys Alexander Ditter, Gabriel Graf, Dietmar Fey
2017	J	`jnl`	Introduction to the special issue on architecture of computing systems. J. Syst. Archit. Frank Hannig, João M. P. Cardoso, Dietmar Fey
2017	—	`conf`	LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. DASIP Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey
2017	C	`conf`	Memristive devices for computing: Beyond CMOS and beyond von Neumann. VLSI-SoC Hoang Anh Du Nguyen, Jintao Yu, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Dietmar Fey
2017	—	`conf`	Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. MEMSYS Mehrdad Biglari, Dietmar Fey
2017	J	`jnl`	Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. Concurr. Comput. Pract. Exp. Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein
2017	—	`conf`	Prototyping memristors in digital system with an FPGA-based testing environment. PATMOS Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Söll, Dietmar Fey
2017	—	`conf`	System on chip generation for multi-sensor and sensor fusion applications. SAMOS Tobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach, Dietmar Fey
2017	—	`conf`	The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs. DASIP Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey
2016	—	`conf`	Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU. SimuTools Bruno Kleinert, Simone Weiß, Franziska Schäfer, Jupiter Bakakeu, Dietmar Fey
2016	—	`conf`	An Application-Specific Instruction Set Processor for Power Quality Monitoring. IPDPS Workshops Steffen Vaas, Marc Reichenbach, Dietmar Fey
2016	—	`conf`	An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors. E2SC@SC Johannes Hofmann, Dietmar Fey
2016	J	`jnl`	An ECM-based energy-efficiency optimization approach for bandwidth-limited streaming kernels on recent Intel Xeon processors. CoRR Johannes Hofmann, Dietmar Fey
2016	—	`conf`	Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks. ARCS Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein
2016	—	`ed.`	Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings ARCS Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
2016	—	`conf`	C++ Classes and Templates for OpenCL Kernels with PATOS. IWOCL Franz Richter-Gottfried, Patrick Kreutzer, Alexander Ditter, Max Schneider, Dietmar Fey
2016	C	`conf`	Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware. SIMULTECH Dominik Schoenwetter, Alexander Ditter, Vadym Aizinger, Balthasar Reuter, Dietmar Fey
2016	—	`conf`	Closing the Performance Gap with Modern C++. ISC Workshops Thomas Heller, Hartmut Kaiser, Patrick Diehl, Dietmar Fey, Marc Alexander Schweitzer
2016	—	`conf`	Dataflow optimization for programmable embedded image preprocessing accelerators. ReConFig Tobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey
2016	Misc	`conf`	Evaluating Performance and Energy-Efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures. ICCS Arne Hendricks, Thomas Heller, Andreas Schäfer, Maximilian Kasparek, Dietmar Fey
2016	—	`conf`	Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. ARC Konrad Häublein, Christian Hartmann, Marc Reichenbach, Dietmar Fey
2016	C	`conf`	Hardware-software Co-simulation of Self-organizing Smart Home Networks - Who am I and Where Are the Others?. SIMULTECH Bruno Kleinert, Franziska Schäfer, Jupiter Bakakeu, Simone Weiß, Dietmar Fey
2016	—	`conf`	Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich
2016	—	`conf`	Improving instruction accurate simulation for parallel automotive applications. SIES Dominik Schoenwetter, Alexander Ditter, Dietmar Fey, Ralph Mader
2016	B	`conf`	Investigation of strategies for an increasing population size in multi-objective CMA-ES. CEC Steffen Limmer, Dietmar Fey
2016	J	`jnl`	Performance analysis of the Kahan-enhanced scalar product on current multi- and manycore processors. CoRR Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein
2016	—	`conf`	Teaching heterogeneous computer architectures using smart camera systems. EWME Benjamin Pfundt, Marc Reichenbach, Christian Hartmann, Konrad Häublein, Dietmar Fey
2016	—	`conf`	The AllScale Runtime Interface - Theoretical Foundation and Concept. MTAGS@SC Arne Hendricks, Thomas Heller, Herbert Jordan, Peter Thoman, Thomas Fahringer, Dietmar Fey
2016	—	`conf`	The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. ReConFig Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey
2016	—	`conf`	Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. MEMSYS Dietmar Fey, Marc Reichenbach, Christopher Söll, Mehrdad Biglari, Jürgen Röber, Robert Weigel
2015	J	`jnl`	A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures. CoRR Christian Hartmann, Anna Yupatova, Marc Reichenbach, Dietmar Fey, Reinhard German
2015	J	`jnl`	Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks. CoRR Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein
2015	B	`conf`	Architecture and simulation of a hybrid memristive multiplier network using redundant number representation. IJCNN Dietmar Fey, Jonathan Martschinke
2015	J	`jnl`	Automatic Optimization of Hardware Accelerators for Image Processing. CoRR Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey
2015	—	`conf`	Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing. IPDPS Workshops Christian Herglotz, Jürgen Seiler, André Kaup, Arne Hendricks, Marc Reichenbach, Dietmar Fey
2015	J	`jnl`	Execution-Cache-Memory Performance Model: Introduction and Validation. CoRR Johannes Hofmann, Jan Eitzinger, Dietmar Fey
2015	—	`conf`	FAUPU - A design framework for the development of programmable image processing architectures. ReConFig Marc Reichenbach, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey
2015	—	`conf`	FREACSIM: a framework for creating and simulating real-time capable network on chip systems and applications. SimuTools Dominik Schoenwetter, Ronald Veldema, Dietmar Fey
2015	—	`conf`	Framework for parameter analysis of FPGA-based image processing architectures. SAMOS Marc Reichenbach, Benjamin Pfundt, Dietmar Fey
2015	—	`conf`	Hardware-software co-simulation for medical x-ray control units. SimuTools Bruno Kleinert, Gholam Reza Rahimi, Marc Reichenbach, Dietmar Fey
2015	—	`conf`	Higher-level parallelization for local and distributed asynchronous task-based programming. ESPM@SC Hartmut Kaiser, Thomas Heller, Daniel Bourgeois, Dietmar Fey
2015	J	`jnl`	OpenCL 2.0 for FPGAs using OCLAcc. CoRR Franz Richter-Gottfried, Alexander Ditter, Dietmar Fey
2015	—	`conf`	Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors. PPAM (1) Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein
2015	J	`jnl`	Performance analysis of the Kahan-enhanced scalar product on current multicore processors. CoRR Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein
2015	J	`jnl`	Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). CoRR Frank Hannig, Dietmar Fey, Anton Lokhmotov
2015	—	`conf`	Real-time correlation for locating systems utilizing heterogeneous computing architectures. DASIP Marc Reichenbach, Maximilian Kasparek, Mohammad Alawieh, Konrad Häublein, Dietmar Fey
2015	Misc	`conf`	SmartEco: An Integrated Solution from Load Balancing between the Grid and Consumers to Local Energy Efficiency. UCC Alexander Ditter, Dietmar Fey, Johannes Burner, Jörg Franke
2015	J	`jnl`	Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey
2015	C	`conf`	Tsunami and Storm Surge Simulation Using Low Power Architectures - Concept and Evaluation. SIMULTECH Dominik Schoenwetter, Alexander Ditter, Bruno Kleinert, Arne Hendricks, Vadym Aizinger, Harald Köstler, Dietmar Fey
2015	—	`conf`	Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures. SIMULTECH (Selected Papers) Dominik Schoenwetter, Alexander Ditter, Bruno Kleinert, Arne Hendricks, Vadym Aizinger, Dietmar Fey
2014	—	`conf`	A Generic Approach for Analysis of White-Light Interferometry Data via User-Defined Algorithms. ICCSA (4) Max Schneider, Dietmar Fey, Kay Wenzel, Torsten Machleidt
2014	—	`conf`	A Portable Petascale Framework for Efficient Particle Methods with Custom Interactions. EuroMPI/ASIA Andreas Schäfer, Thomas Heller, Dietmar Fey
2014	—	`conf`	Designing and manufacturing of real embedded multi-core CPUs: A holistic teaching approach in computer architecture. EWME Marc Reichenbach, Benjamin Pfundt, Dietmar Fey
2014	—	`conf`	Fast and generic hardware architecture for stereo block matching applications on embedded systems. ReConFig Konrad Häublein, Marc Reichenbach, Dietmar Fey
2014	J	`jnl`	Fast image processing for optical metrology utilizing heterogeneous computer architectures. Comput. Electr. Eng. Marc Reichenbach, Ralf Seidler, Benjamin Pfundt, Dietmar Fey
2014	—	`conf`	HPX: A Task Based Programming Model in a Global Address Space. PGAS Hartmut Kaiser, Thomas Heller, Bryce Adelstein-Lelbach, Adrian Serio, Dietmar Fey
2014	—	`conf`	On the Way to Big Data Applications in Industrial Computed Tomography. BigData Congress Alexander Ditter, Dietmar Fey, Tobias Schön, Steven Oeckl
2014	—	`conf`	Performance Investigation and Tuning in the Interoperable Cloud4E Platform. Euro-Par Workshops (2) Steffen Limmer, Maik Srba, Dietmar Fey
2014	J	`jnl`	Services for numerical simulations and optimisations in grids. Int. J. Parallel Emergent Distributed Syst. Steffen Limmer, André Schneider, Christian Boehme, Dietmar Fey, Simon Schmitz, Achim Graupner, Martin Sülzle
2013	C	`conf`	An auto-tuning approach for optimizing base operators for non-destructive testing applications on heterogeneous multi-core architectures. ISORC Thomas Heller, Dietmar Fey, Markus Rehak
2013	J	`jnl`	Performance investigations of genetic algorithms on graphics cards. Swarm Evol. Comput. Johannes Hofmann, Steffen Limmer, Dietmar Fey
2013	—	`conf`	Smart sensor architectures for embedded biosignal analysis. DASIP Benjamin Pfundt, Marc Reichenbach, Björn M. Eskofier, Dietmar Fey
2013	—	`conf`	Using HPX and LibGeoDecomp for scaling HPC applications on heterogeneous supercomputers. ScalA@SC Thomas Heller, Hartmut Kaiser, Andreas Schäfer, Dietmar Fey
2012	—	`conf`	A Generic VHDL Template for 2D Stencil Code Applications on FPGAs. ISORC Workshops Michael Schmidt, Marc Reichenbach, Dietmar Fey
2012	—	`conf`	A Predictive Performance Model for Stencil Codes on Multicore CPUs. VECPAR Andreas Schäfer, Dietmar Fey
2012	—	`conf`	A Speed-Up Study for a Parallelized White Light Interferometry Preprocessing Algorithm on a Virtual Embedded Multiprocessor System. ARCS Workshops Dominik Schoenwetter, Max Schneider, Dietmar Fey
2012	—	`conf`	Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAs. ReConFig Michael Schmidt, Dietmar Fey
2012	C	`conf`	Competence model for embedded micro-and nanosystems. EDUCON André Schäfer, Rainer Brück, Bruno Kleinert, Harald Schmidt, Dietmar Fey, Steffen Büchner, Steffen Jaschke, Sigrid E. Schubert
2012	B	`conf`	Evolutionary Design of Active Free Space Optical Networks Based on Digital Mirror Devices. EvoApplications Steffen Limmer, Dietmar Fey, Ulrich Lohmann, Jürgen Jahns
2012	—	`conf`	Heterogeneous computer architectures: An image processing pipeline for optical metrology. ReConFig Marc Reichenbach, Ralf Seidler, Dietmar Fey
2012	J	`jnl`	Optical multiplexing techniques for photonic Clos networks in High Performance Computing Architectures. J. Supercomput. Dietmar Fey, Max Schneider, Jürgen Jahns, Hans Knuppertz
2012	—	`conf`	Optimization of a Short-Range Proximity Effect Correction Algorithm in E-Beam Lithography Using GPGPUs. ICA3PP (1) Max Schneider, Nikola Belic, Christoph Sambale, Ulrich Hofmann, Dietmar Fey
2012	J	`jnl`	Realizing real-time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware. Concurr. Comput. Pract. Exp. Dietmar Fey, Marc Reichenbach, Marcus Komann, Ralf Seidler
2012	B	`conf`	The empirically refined competence structure model for embedded micro- and nanosystems. ITiCSE André Schäfer, Rainer Brück, Steffen Büchner, Steffen Jaschke, Sigrid E. Schubert, Dietmar Fey, Bruno Kleinert, Harald Schmidt
2012	—	`conf`	Zero-Overhead Interfaces for High-Performance Computing Libraries and Kernels. SC Companion Andreas Schäfer, Dietmar Fey
2011	B	`conf`	A normative competence structure model for embedded micro- and nanosystems development. ITiCSE André Schäfer, Rainer Brück, Steffen Jaschke, Sigrid E. Schubert, Dietmar Fey, Bruno Kleinert, Harald Schmidt
2011	—	`conf`	Analytical Model for the Optimization of Self-Organizing Image Processing Systems Utilizing Cellular Automata. ISORC Workshops Marc Reichenbach, Michael Schmidt, Dietmar Fey
2011	—	`conf`	Competence research: teaching embedded micro/nano systems. WESE Steffen Jaschke, Sigrid E. Schubert, André Schäfer, Rainer Brück, Bruno Kleinert, Harald Schmidt, Dietmar Fey
2011	—	`ch.`	Emergent Computing with Marching Pixels for Real-Time Smart Camera Applications. Organic Computing Dietmar Fey, Marcus Komann
2011	A	`conf`	Evolutionary optimization of layouts for high density free space optical network links. GECCO Steffen Limmer, Dietmar Fey, Ulrich Lohmann, Jürgen Jahns
2011	—	`ch.`	Generic Emergent Computing in Chip Architectures. Organic Computing Marc Reichenbach, Ralf Seidler, Dietmar Fey, Benjamin Pfundt
2011	Misc	`conf`	High Performance Stencil Code Algorithms for GPGPUs. ICCS Andreas Schäfer, Dietmar Fey
2011	—	`conf`	Parallel simulation of dendritic growth on unstructured grids. IA3@SC Andreas Schäfer, Julian Hammer, Dietmar Fey
2011	Misc	`conf`	Performance comparison of designated preprocessing white light interferometry algorithms on emerging multi- and many-core architectures. ICCS Max Schneider, Dietmar Fey, Daniel Kapusi, Torsten Machleidt
2010	—	`conf`	An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels. ReConFig Michael Schmidt, Dietmar Fey
2010	C	`conf`	Dynamically Programmable Image Processor for Compact Vision Systems. CIT Andreas Loos, Michael Schmidt, Dietmar Fey, Jens Grobel
2010	—	`conf`	Framework for Distributed Evolutionary Algorithms in Computational Grids. ISICA (1) Steffen Limmer, Dietmar Fey
2010	—	`conf`	Marching Pixels - Rechnen mit Hardware-Agenten im 2D Pixelraum. GI Jahrestagung (2) Dietmar Fey
2010	—	`conf`	Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities. HPCS Matthias Sand, Volkmar Sieh, Dietmar Fey
2010	—	`conf`	Realizing Real-Time Centroid Detection of Multiple Objects with Marching Pixels Algorithms. ISORC Workshops Dietmar Fey, Marcus Komann, Marc Reichenbach, Ralf Seidler
2010	—	`conf`	Revising the Trade-off between the Number of Agents and Agent Intelligence. EvoApplications (1) Marcus Komann, Dietmar Fey
2010	Misc	`conf`	Seamless high speed simulation of VHDL components in the context of comprehensive computing systems using the virtual machine faumachine. WSC Stefan Potyra, Matthias Sand, Volkmar Sieh, Dietmar Fey
2010	—	`conf`	Simulation and Optimized Design of High Density Optical Crossconnect Systems for Massively Parallel Computing Architectures. OSC Ulrich Lohmann, Jürgen Jahns, Steffen Limmer, Dietmar Fey
2010	J	`jnl`	Unconventional Computing - Reversible Signed Digit Adders for Future Nanocomputing Devices (Unkonventionelles Rechnen - reversible Addierer für künftiges Nanocomputing). it Inf. Technol. Dietmar Fey, Steffen Limmer
2009	—	`conf`	Distributed vision with smart pixels. SCG Sándor P. Fekete, Dietmar Fey, Marcus Komann, Alexander Kröller, Marc Reichenbach, Christiane Schmidt
2009	A	`conf`	Evaluating the evolvability of emergent agents with different numbers of states. GECCO Marcus Komann, Dietmar Fey
2009	—	`conf`	Herausforderungen der Technischen Informatik beim Unkonventionellen Rechnen. GI Jahrestagung Dietmar Fey
2009	C	`conf`	Model-Driven Design and Organic Computing -- Two Different but Possibly Accordable Concepts for the Design of Embedded Systems. ISORC Dietmar Fey
2009	B	`conf`	On the Effectiveness of Evolution Compared to Time-Consuming Full Search of Optimal 6-State Automata. EuroGP Marcus Komann, Patrick Ediger, Dietmar Fey, Rolf Hoffmann
2009	—	`conf`	Optical Multiplexing Techniques for Photonic Clos Networks in High Performance Computing Architectures. OSC Dietmar Fey, Max Schneider, Jürgen Jahns, Hans Knuppertz
2008	—	`conf`	A Profitability Heuristic that Reduces the Parameter Dependence of Dynamic Load Balancing. Informatiktage Jakob Erdmann, Andreas Schäfer, Christian Kauhaus, Dietmar Fey
2008	—	`conf`	Challenges of MPI over IPv6. ICNS Adrian Knoth, Christian Kauhaus, Dietmar Fey, Lars Schneidenbach, Bettina Schnor
2008	—	`conf`	Emergent algorithms for centroid and orientation detection in high-performance embedded cameras. Conf. Computing Frontiers Marcus Komann, Alexander Kröller, Christiane Schmidt, Dietmar Fey, Sándor P. Fekete
2008	—	`conf`	LibGeoDecomp: A Grid-Enabled Library for Geometric Decomposition Codes. PVM/MPI Andreas Schäfer, Dietmar Fey
2008	—	`conf`	Pollarder: An Architecture Concept for Self-adapting Parallel Applications in Computational Science. ICCS (1) Andreas Schäfer, Dietmar Fey
2008	—	`conf`	Solving the problem of enforced restriction to few states while evolving cellular automata. Automata Marcus Komann, Dietmar Fey
2007	—	`conf`	A Virtual Test Environment for MPI Development: Quick Answers to Many Small Questions. PVM/MPI Wolfgang Schnerring, Christian Kauhaus, Dietmar Fey
2007	C	`conf`	An Organic Computing architecture for visual microprocessors based on Marching Pixels. ISCAS Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos
2007	B	`conf`	Comparison of Evolving Uniform, Non-uniform Cellular Automaton, and Genetic Programming for Centroid Detection with Hardware Agents. PaCT Marcus Komann, Andreas Mainka, Dietmar Fey
2007	J	`jnl`	Realising emergent image preprocessing tasks in cellular-automaton-alike massively parallel hardware. Int. J. Parallel Emergent Distributed Syst. Marcus Komann, Dietmar Fey
2006	—	`conf`	A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems. PARELEC Michael Schmidt, Andreas Loos, Dietmar Fey
2006	—	`conf`	Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach. PARELEC Christian Kauhaus, Dietmar Fey
2006	—	`conf`	Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware. PARELEC Marcus Komann, Dietmar Fey
2006	—	`conf`	Parallelization of Simulations for Various Magnetic System Models on Small-Sized Cluster Computers with MPI. ICCSA (5) Frank Schurz, Dietmar Fey, Dmitri Berkov
2006	B	`conf`	SOGOS - A Distributed Meta Level Architecture for the Self-Organizing Grid of Services. MDM Clemens Beckstein, Peter Dittrich, Christian Erfurth, Dietmar Fey, Birgitta König-Ries, Martin Mundhenk, Harald Sack
2005	—	`ed.`	18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005 ARCS Workshops Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Christian Hochberger, Thomas Martinetz, Christian Müller-Schloer, Hartmut Schmeck, Theo Ungerer, Rolf P. Würtz
2005	—	`conf`	Calculation of Single-File Diffusion Using Grid-Enabled Parallel Generic Cellular Automata Simulation. PVM/MPI Marcus Komann, Christian Kauhaus, Dietmar Fey
2005	—	`conf`	Marching Pixels: A new Organic Computing Prinicple for Smart CMOS Camera Chips. ARCS Workshops Dietmar Fey, Daniel Schmidt
2005	—	`conf`	Marching-pixels: a new organic computing paradigm for smart sensor processor arrays. Conf. Computing Frontiers Dietmar Fey, Daniel Schmidt
2004	—	`conf`	A Framework for Optimising Parameter Studies on a Cluster Computer by the Example of Micro-system Design. PVM/MPI Dietmar Fey, Marcus Komann, Christian Kauhaus
2004	—	`ed.`	ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany ARCS Workshops Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, Thomas A. Runkler
2004	—	`conf`	Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras. ARCS Workshops Dietmar Fey, Daniel Schmidt, Andreas Loos
2004	—	`conf`	Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips. PARELEC Dietmar Fey, Lutz Hoppe, Andreas Loos
2003	J	`jnl`	OptoRAP - eine rekonfigurierbare optoelektronische Parallelprozessor-Architektur für die Bildvorverarbeitung (OptoRAP - a Reconfigurable Optoelectronic Parallel Processor Architecture for Image Pre-Processing). it Inf. Technol. Dietmar Fey, Andreas Loos
2003	J	`jnl`	Optotechnologie in der IT. it Inf. Technol. Dietmar Fey
2002	—	`book`	Optik in der Rechentechnik - photonisches VLSI und optische Netzwerke. Dietmar Fey
2001	J	`jnl`	A digital multi-layer-perceptron hardware architecture based on three dimensional massively parallel optoelectronic circuits. Informatica (Slovenia) Klaus D. Maier, Clemens Beckstein, Reinhard Blickhan, Dietmar Fey, Werner Erhard
2000	J	`jnl`	Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits. J. Supercomput. Dietmar Fey, Marko Degenkolb
2000	J	`jnl`	Optical interconnects for neural and reconfigurable VLSI architectures. Proc. IEEE Dietmar Fey, Werner Erhard, Matthies Gruber, Jürgen Jahns, Hartmut Bartelt, Guido Grimm, Lutz Hoppe, Stefan Sinzinger
1999	—	`conf`	3D Optoelectronic Fix Point Unit and Its Advantages Processing 3D Data. Euro-Par Bernd Kasche, Dietmar Fey, T. Höhn, Werner Erhard
1999	J	`jnl`	Architekturen und Entwurfssysteme für ein optoelektronisches 3-D VLSI. Informationstechnik Tech. Inform. Dietmar Fey, Werner Erhard
1999	—	`conf`	Massively Parallel Volume Rendering by Exploiting a 3d Optoelectronic Arithmetic Logical Unit. ARCS Bernd Kasche, Dietmar Fey, T. Höhn, Werner Erhard
1996	—	`conf`	Principles for Optoelectronic 3D Architectures and Correponding Algorithms to Calculate Standard Functions. Parcella Bernd Kasche, Dietmar Fey
1996	—	`conf`	Transformation of a 2-D VLSI Systolic Adder Circuit in 3-D Circuits Using Optical Interconnections. Euro-Par, Vol. II Dietmar Fey
1994	—	`book`	Parallele digitale optische Recheneinheiten - Modellierung, Simulation und Bewertung. Werner Erhard, Dietmar Fey
1993	—	`—`	Modellierung, Simulation und Bewertung paralleler digitaler optischer Systeme. Dietmar Fey
1992	—	`conf`	Architekturkonzepte für massiv-parallele, opto-elektronische Rechnersysteme. ARCS Dietmar Fey, Konrad Zürl, A. Hetzner