Didier Née

11 papers A 4Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2011 J jnl
Back-end soft and hard defect monitoring using a single test chip.
Microelectron. Reliab.
Fabrice Rigaud, Jean-Michel Portal, Hassen Aziza, Didier Née, Julien Vast, Fabrice Argoud, Bertrand Borot
2007 J jnl
A New Embedded Measurement Structure for eDRAM Capacitor
CoRR
Laurent Lopez, Jean-Michel Portal, Didier Née
2005 A conf
A New Embedded Measurement Structure for eDRAM Capacitor.
DATE
Laurent Lopez, Jean-Michel Portal, Didier Née
2005 J jnl
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement.
J. Electron. Test.
Jean-Michel Portal, Hassen Aziza, Didier Née
2005 — conf
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring.
DFT
B. Saillet, Jean-Michel Portal, Didier Née
2003 A conf
EEPROM Memory: Threshold Voltage Built In Self Diagnosis.
ITC
Jean-Michel Portal, Hassen Aziza, Didier Née
2003 A conf
Infrastructure IP for Back-End Yield Improvement.
ITC
L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot
2002 — conf
An Automated Design Methodology for EEPROM Cell (ADE).
MTDT
Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née
2002 A conf
An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell.
ITC
Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née
2002 — conf
Floating-gate EEPROM cell model based on MOS model 9.
ISCAS (3)
Jean-Michel Portal, L. Forli, Didier Née
2002 — conf
Floating-gate EEPROM cell: threshold voltage sensibility to geometry.
ISCAS (1)
Jean-Michel Portal, L. Forli, Didier Née