Didier Lattard

47 papers A 4B 2C 6Misc 1Journal 8Unranked 25

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. VLSI Technology and Circuits J. Luge-Alvarez, J. B. David, Alexandre Siligaris, Vincent Puyal, G. Moritz, Tadeu Mota Frutuoso, V. Lapras, Claire Fenouillet-Béranger, Laurent Brunet, P. Vincent, Didier Lattard, Xavier Garros, François Andrieu, Perrine Batude
2021	J	`jnl`	IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2020	—	`conf`	2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm ISSCC Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2020	A	`conf`	M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. DATE Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard
2020	J	`jnl`	Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu
2019	A	`conf`	Advanced 3D Technologies and Architectures for 3D Smart Image Sensors. DATE Pascal Vivet, Gilles Sicard, Laurent Millet, Stéphane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sébastien Thuries, Didier Lattard, Séverine Cheramy, Perrine Batude, Fabien Clermidy
2019	—	`conf`	Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. 3DIC Olivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, Mehdi Mouhdach, Sébastien Thuries, Pascal Vivet
2019	—	`conf`	Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 3DIC Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
2019	B	`conf`	Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné
2018	—	`conf`	A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet
2018	—	`conf`	A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. ICICDT François Andrieu, Perrine Batude, Laurent Brunet, Claire Fenouillet-Béranger, Didier Lattard, Sébastien Thuries, Olivier Billoint, Richard Fournel, Maud Vinet
2018	B	`conf`	BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. ETS Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
2018	—	`conf`	Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability. IRPS Lucile Arnaud, Stéphane Moreau, Amadine Jouve, Imed Jani, Didier Lattard, Frank Fournel, C. Euvrard, Y. Exbrayat, Viorel Balan, Nicolas Bresson, S. Lhostis, J. Jourdon, E. Deloffre, S. Guillaumet, Alexis Farcy, Simon Gousseau, M. Arnoux
2018	—	`conf`	Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude
2017	J	`jnl`	A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel
2017	—	`conf`	Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. NEWCAS Imed Jani, Didier Lattard, Pascal Vivet, Edith Beigné
2016	—	`conf`	8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos
2016	J	`jnl`	Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. IEEE Des. Test Perceval Coudrain, Papa Momar Souare, Rafael Prieto, Vincent Fiori, Alexis Farcy, Laurent Le Pailleur, Jean-Philippe Colonna, Cristiano Santos, Pascal Vivet, M. Haykel Ben Jamaa, Denis Dutoit, François de Crecy, Sylvain Dumas, Christian Chancel, Didier Lattard, Séverine Cheramy
2016	—	`conf`	ITAC: A complete 3D integration test platform. 3DIC Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau, Karim Azizi-Mourier, C. Chantre, Pascal Vivet, Gaël Pillonnet, F. Casset, F. Ponthenier, Alexis Farcy, S. Lhostis, Jean Michailos, Alexandre Arriordaz, Séverine Cheramy
2015	—	`conf`	3D advanced integration technology for heterogeneous systems. 3DIC Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy
2015	C	`conf`	An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs. ISCAS Vincent Lenoir, Didier Lattard, Ahmed Amine Jerraya
2015	—	`conf`	Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB. NEWCAS Vincent Lenoir, Warody Lombardi, Didier Lattard, Ahmed Amine Jerraya
2015	C	`conf`	Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet
2014	—	`conf`	Computational load reduction by downsampling for energy-efficient digital baseband. NEWCAS Vincent Lenoir, Didier Lattard, Francois Dehmas, Dominique Morche, Ahmed Amine Jerraya
2014	—	`conf`	Non-coherent detection of M-ary orthogonal signals using Compressive Sensing. CSNDSP Vincent Lenoir, Didier Lattard, Francois Dehmas, Dominique Morche, Ahmed Amine Jerraya
2012	J	`jnl`	A Stackable LTE Chip for Cost-effective 3D Systems. IPSJ Trans. Syst. LSI Des. Methodol. Walid Lafi, Didier Lattard, Ahmed Amine Jerraya
2012	—	`conf`	Algorithm architecture co-design for ultra low-power image sensor. Sensors, Cameras, and Systems for Industrial and Scientific Applications Timothé Laforest, Antoine Dupret, Arnaud Verdant, Didier Lattard, Patrick Villard
2012	J	`jnl`	An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip. Softw. Pract. Exp. Walid Lafi, Didier Lattard, Ahmed Amine Jerraya
2011	A	`conf`	A 3D reconfigurable platform for 4G telecom applications. DATE Walid Lafi, Didier Lattard, Ahmed Amine Jerraya
2010	—	`conf`	A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio. ISVLSI Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres
2010	C	`conf`	An efficient hierarchical router for large 3D NoCs. International Symposium on Rapid System Prototyping Walid Lafi, Didier Lattard, Ahmed Amine Jerraya
2010	C	`conf`	Flexible and distributed real-time control on a 4G telecom MPSoC. ISCAS Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres
2010	A	`conf`	Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. DATE Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres
2009	—	`conf`	High level modelling and performance evaluation of address mapping in NAND flash memory. ICECS Walid Lafi, Didier Lattard, Ahmed Amine Jerraya
2008	J	`jnl`	A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. IEEE J. Solid State Circuits Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens
2008	—	`conf`	A flexible modeling and simulation framework for Design Space Exploration. SoC Camille Jalier, Didier Lattard, Gilles Sassatelli
2008	—	`conf`	An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications. ESSCIRC Carolynn Bernier, Frédéric Hameau, Gérard Billiot, Emeric de Foucauld, Stéphanie Robinet, Didier Lattard, Jean Durupt, Francois Dehmas, Laurent Ouvry, Pierre Vincent
2007	—	`conf`	A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens
2007	—	`conf`	Trends in complex SoC Design: From technology variability to multiprocessor architectures. ICECS Didier Lattard
2005	C	`conf`	Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. IEEE International Workshop on Rapid System Prototyping Romain Lemaire, Fabien Clermidy, Yves Durand, Didier Lattard, Ahmed Amine Jerraya
2005	—	`conf`	Proposition of a benchmark for evaluation of cores mapping onto NoC architectures. ReCoSoC Julien Delorme, Dominique Houzet, Romain Lemaire, Didier Lattard
1996	C	`conf`	A Data Dependent Architecture Based on Seeded Region Growing Strategy for Advanced Morphological Operators. ISMM Dominique Noguet, Alain Merle, Didier Lattard
1991	J	`jnl`	A VLSI implementation of parallel image reconstruction. CVGIP Graph. Model. Image Process. Didier Lattard, Guy Mazaré
1990	—	`conf`	Massively parallel architecture: application to neural net emulation and image reconstruction. ASAP Didier Lattard, Bernard Faure, Guy Mazaré
1989	—	`—`	Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction). Didier Lattard
1988	Misc	`conf`	An Integrated Asynchronous Cellular Array to Do Parallel Image Reconstruction. MVA Didier Lattard, Guy Mazaré
1988	—	`conf`	An Integrated Highly Parallel Architecture for Image Reconstruction. Advances in Computer Graphics Hardware Didier Lattard, Guy Mazaré