Di Li

33 papers Journal 33
YearRankTypeTitle / Venue / Authors
2026 J jnl
Efficient Floorplan Optimization Design for Collaborative Control of Thermal Reliability and Interconnect Distance in Ultrawideband System.
IEEE Trans. Reliab.
Jiaming Su, Xianglong Wang, Yunqi Yang, Dongdong Chen, Di Li, Yintang Yang
2026 J jnl
RL Algorithm-Based Optimization Design of 16-bit ΣΔ ADC for High-Precision Smart Sensor System.
IEEE Internet Things J.
Yunqi Yang, Daoming Zhang, Wenlong Xu, Dongdong Chen, Qidong Zhang, Di Li, Shibing Zhang, Yintang Yang
2025 J jnl
A High-Accuracy 3-D Ultrawideband Positioning Approach Using Clustering Optimization Algorithm and Error-Correction Model.
IEEE Trans. Instrum. Meas.
Xianglong Wang, Daoming Zhang, Yunqi Yang, Dongdong Chen, Di Li, Qidong Zhang, Yintang Yang
2025 J jnl
A High-Efficiency Codesign Method for Bandgap Circuit by Submodule Optimization.
Int. J. Circuit Theory Appl.
Yunqi Yang, Dongdong Chen, Xianglong Wang, Di Li, Yintang Yang
2025 J jnl
Intelligent Optimization Design of GS-TSV With RDLs for Chiplet-Based Integrated System in IoT.
IEEE Internet Things J.
Yawen Cui, Xianglong Wang, Dongdong Chen, Di Li, Yintang Yang
2025 J jnl
Recent Developments and Perspectives on Optimization Design Methods for Analog Integrated Circuits.
Symmetry
Yunqi Yang, Jiaming Su, Xiaoran Lai, Dongdong Chen, Di Li, Yintang Yang
2025 J jnl
The High-Efficiency Lightweight Optimization Method for Analog-to-Digital Conversion System in IoT.
IEEE Internet Things J.
Yunqi Yang, Lei Liu, Dongdong Chen, Di Li, Yintang Yang
2024 J jnl
Research on Si/SiO2 Interfaces Characteristics Under Service Conditions.
Symmetry
Weida Zhang, Yunqi Yang, Dongdong Chen, Tianlong Zhao, Di Li, Yintang Yang
2024 J jnl
The High-Efficiency Optimization Design Method for Two-Stage Miller Compensated Operational Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Yunqi Yang, Xiaoyu Yin, Dongdong Chen, Di Li, Yintang Yang
2023 J jnl
A High-Efficiency Design Method of TSV Array for Thermal Management of 3-D Integrated System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xianglong Wang, Yintang Yang, Dongdong Chen, Di Li
2023 J jnl
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Kexu Chen, Di Li, Dongdong Chen, Changchun Chai
2023 J jnl
An improved Fourier Ptychography algorithm for ultrasonic array imaging.
Comput. Biol. Medicine
Yaoyao Yang, Runcong Wu, Dongdong Chen, Chunlong Fei, Di Li, Yintang Yang
2023 J jnl
The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System.
Symmetry
Xianglong Wang, Dongdong Chen, Di Li, Chen Kou, Yintang Yang
2023 J jnl
Thermal-Stress Coupling Optimization for Coaxial through Silicon Via.
Symmetry
Dongdong Chen, Yintang Yang, Xianglong Wang, Di Li, Yi Liang, Changqing Xu
2022 J jnl
An Improved Indoor 3-D Ultrawideband Positioning Method by Particle Swarm Optimization Algorithm.
IEEE Trans. Instrum. Meas.
Yintang Yang, Xianglong Wang, Di Li, Dongdong Chen, Qidong Zhang
2022 J jnl
Optimized Backing Layers Design for High Frequency Broad Bandwidth Ultrasonic Transducer.
IEEE Trans. Biomed. Eng.
Chenxue Hou, Chunlong Fei, Zhaoxi Li, Shuxiao Zhang, Jiujing Man, Dongdong Chen, Runcong Wu, Di Li, Yintang Yang, Wei Feng
2021 J jnl
Analysis and Design of Low-Complexity Stochastic DEM Encoder for Reduced-Distortion Multi-bit DAC in Sigma-Delta Modulators.
Circuits Syst. Signal Process.
Di Li, Chunlong Fei, Qidong Zhang
2020 J jnl
A 20-MHz BW MASH Sigma-Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs.
J. Circuits Syst. Comput.
Di Li, Chunlong Fei, Qidong Zhang, Yani Li, Yintang Yang
2020 J jnl
An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique.
IEICE Electron. Express
Yi Yang, Di Li, Chanrong Jiang, Yuqian Liu, Yintang Yang
2020 J jnl
High Resolution ADC for Ultrasound Color Doppler Imaging Based on MASH Sigma-Delta Modulator.
IEEE Trans. Biomed. Eng.
Di Li, Xuejun Qian, Runze Li, Chunlong Fei, Laiming Jiang, Xuyuan Chen, Yintang Yang, Qifa Zhou
2019 J jnl
A 15-MHz bandwidth double sampling MASH25b-15b sigma-delta modulator with DEM for multibit DACs.
Int. J. Circuit Theory Appl.
Di Li, Chunlong Fei, Qidong Zhang, Yani Li, Xiaopeng Wu, Yintang Yang
2019 J jnl
A 6-bit digital CMOS variable gain attenuator with large dynamic range and high linearity-in-dB for ultrasound imaging applications.
Microelectron. J.
Di Li, Chunlong Fei, Xiaopeng Wu, Yintang Yang
2019 J jnl
A large dynamic range voltage controlled attenuator with improved linearity-in-dB for ultrasound applications.
Int. J. Circuit Theory Appl.
Di Li, Chunlong Fei, Yani Li, Qidong Zhang, Yintang Yang
2019 J jnl
Mismatch errors randomization for multi-bit DAC in sigma-delta modulators based on butterfly-type network.
Microelectron. J.
Di Li, Chunlong Fei, Qidong Zhang, Yani Li, Yintang Yang
2016 J jnl
A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications.
J. Circuits Syst. Comput.
Zuo-Chen Shi, Yintang Yang, Di Li, Yang Liu
2016 J jnl
A large dynamic-range, high dB-linearity VGA using switch arrays and second-order mismatch-shaping DEM technique.
Int. J. Circuit Theory Appl.
Di Li, Yintang Yang, Zuo-Chen Shi, Zhan Jing
2016 J jnl
An IM2-free floating current buffer using average power based automatic calibration for IEEE 802.15.6 transmitter.
IEICE Electron. Express
Yang Liu, Yintang Yang, Di Li, Zuo-Chen Shi
2016 J jnl
Design of a fully integrated receiver analog baseband chain for 2.4-GHz ZigBee applications.
Microelectron. J.
Yintang Yang, Zuo-Chen Shi, Di Li, Yu Wang
2015 J jnl
A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications.
Microelectron. J.
Di Li, Yintang Yang, Zhangming Zhu, Zuo-Chen Shi
2015 J jnl
A low-distortion multi-bit sigma-delta ADC with mismatch-shaping DACs for WLAN applications.
Microelectron. J.
Di Li, Yintang Yang, Zuo-Chen Shi, Yang Liu
2014 J jnl
A fully integrated feedback AGC loop for ZigBee (IEEE 802.15.4) RF transceiver applications.
Microelectron. J.
Di Li, Yintang Yang, Zhan Jing, Zuo-Chen Shi, Yang Liu
2014 J jnl
Design of a Fully Integrated 2.4 GHz frequency PLL synthesizer for ZigBee Transceiver Application.
J. Circuits Syst. Comput.
Di Li, Yintang Yang, Duan Zhou, Yani Li, Xiaopeng Wu
2010 J jnl
Design of a low power GPS receiver in 0.18 µm CMOS technology with a SigmaDeltafractional-N synthesizer.
J. Zhejiang Univ. Sci. C
Di Li, Yintang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qiankun Liu, Da-Long Zhang