Dhruva Acharyya

17 papers A* 4A 4Misc 1Journal 4Unranked 4

Year	Rank	Type	Title / Venue / Authors
2013	A*	`conf`	A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. DAC Raj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic
2013	—	`conf`	Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. HOST Jim Aarestad, Jim Plusquellic, Dhruva Acharyya
2013	J	`jnl`	HELP: A Hardware-Embedded Delay PUF. IEEE Des. Test Jim Aarestad, Philip Ortiz, Dhruva Acharyya, Jim Plusquellic
2011	A	`conf`	Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. ITC Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson
2011	A*	`conf`	Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal
2011	—	`conf`	Measuring within-die spatial variation profile through power supply current measurements. ISQED Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal
2010	J	`jnl`	Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad I IEEE Trans. Inf. Forensics Secur. Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic
2010	A	`conf`	Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic
2010	A*	`conf`	Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. DAC Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
2009	A*	`conf`	A physical unclonable function defined using power distribution system equivalent resistance variations. DAC Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
2009	A	`conf`	Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic
2007	—	`conf`	Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
2007	—	`conf`	Rigorous extraction of process variations for 65nm CMOS design. ESSCIRC Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka
2006	J	`jnl`	Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. IEEE Des. Test Comput. Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel
2005	Misc	`conf`	Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. VTS Dhruva Acharyya, Jim Plusquellic
2003	J	`jnl`	Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. J. Electron. Test. Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic
2003	A	`conf`	Impedance Profile of a Commercial Power Grid and Test System. ITC Dhruva Acharyya, Jim Plusquellic