Dhiraj K. Pradhan

275 papers A* 5A 32B 1C 23Misc 17Journal 115Unranked 81
YearRankTypeTitle / Venue / Authors
2021 J jnl
Design of Single-Bit Fault-Tolerant Reversible Circuits.
IEEE Des. Test
Hari Mohan Gaur, Ashutosh Kumar Singh, Anand Mohan, Masahiro Fujita, Dhiraj K. Pradhan
2017 J jnl
Guest Editorial: Special Issue on "Secure and Fault-Tolerant Embedded Computing".
ACM Trans. Embed. Comput. Syst.
Jimson Mathew, Rajat Subhra Chakraborty, Dhiraj K. Pradhan
2017 J jnl
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits.
IEEE Trans. Reliab.
Mohamad Imran Bin Bandan, Samuel Nascimento Pagliarini, Jimson Mathew, Dhiraj K. Pradhan
2017 J jnl
Selected Articles from the IEEE ISED 2016 Conference.
J. Low Power Electron.
Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan
2016 Misc conf
Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation.
VLSID
Urbi Chatterjee, Rajat Subhra Chakraborty, Jimson Mathew, Dhiraj K. Pradhan
2015 — conf
2T2M memristor based TCAM cell for low power applications.
DTIS
Yuanfan Yang, Jimson Mathew, Marco Ottavi, Salvatore Pontarelli, Dhiraj K. Pradhan
2015 J jnl
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2015 J jnl
A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection.
IEEE Trans. Reliab.
Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan
2015 J jnl
A Novel Memristor-Based Hardware Security Primitive.
ACM Trans. Embed. Comput. Syst.
Jimson Mathew, Rajat Subhra Chakraborty, Durga Prasad Sahoo, Yuanfan Yang, Dhiraj K. Pradhan
2015 J jnl
A novel memristor based physically unclonable function.
Integr.
Jimson Mathew, Rajat Subhra Chakraborty, Durga Prasad Sahoo, Yuanfan Yang, Dhiraj K. Pradhan
2015 — conf
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays.
DFTS
Adedotun A. Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2015 — conf
Fault detection and repair of DSC arrays through memristor sensing.
DFTS
Jimson Mathew, Yuamfam Yang, M. Ottavia, T. Browna, A. Zampettia, A. Di Carloa, A. M. Jabirb, Dhiraj K. Pradhan
2015 J jnl
Selected Articles from the IEEE ISED 2014 Conference.
J. Low Power Electron.
Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan
2014 C conf
A hybrid reliability assessment method and its support of sequential logic modelling.
IOLTS
Samuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner, Dhiraj K. Pradhan
2014 A conf
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance.
DATE
Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li
2014 C conf
A placement strategy for reducing the effects of multiple faults in digital circuits.
IOLTS
Samuel N. Pagliarini, Dhiraj K. Pradhan
2014 A conf
Complementary resistive switch based stateful logic operations using material implication.
DATE
Yuanfan Yang, Jimson Mathew, Dhiraj K. Pradhan, Marco Ottavi, Salvatore Pontarelli
2014 — conf
DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs.
ARC
Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Samuel N. Pagliarini, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad Ahmed Shafik, Georgios Smaragdos, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras
2014 J jnl
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.
J. Low Power Electron.
Luo Sun, Jimson Mathew, Samuel N. Pagliarini, Dhiraj K. Pradhan, Ioannis Sourdis
2014 J jnl
Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System.
J. Low Power Electron.
Mohamad Imran Bin Bandan, Subhasis Bhattacharjee, Dhiraj K. Pradhan, Jimson Mathew
2014 — conf
Using memristor state change behavior to identify faults in photovoltaic arrays.
DFT
Jimson Mathew, Marco Ottavi, Yunfan Yang, Dhiraj K. Pradhan
2014 J jnl
Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis.
IEEE Embed. Syst. Lett.
Yuanfan Yang, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan
2014 — conf
Write scheme for multiple Complementary Resistive Switch (CRS) cells.
PATMOS
Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2013 A conf
A fast and Effective DFT for test and diagnosis of power switches in SoCs.
DATE
Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan
2013 J jnl
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng.
Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir
2013 J jnl
DeSyRe: On-demand system reliability.
Microprocess. Microsystems
Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad A. Shafik, Kim Sunesen, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras
2013 — conf
Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis.
ISED
Mohamad Imran Bin Bandan, Subhasis Bhattacharjee, Rishad A. Shafik, Dhiraj K. Pradhan, Jimson Mathew
2013 — conf
Low Power and Robust Binary Tree SRAM Design for Embedded Systems.
ISED
Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan
2013 — conf
Multinomial Memristor Model for Simulations and Analysis.
ISED
Li Gang, Jimson Mathew, Dhiraj K. Pradhan
2013 C conf
Software Modification Aided Transient Error Tolerance for Embedded Systems.
DSD
Rishad A. Shafik, Gerard K. Rauwerda, Jordy Potman, Kim Sunesen, Dhiraj K. Pradhan, Jimson Mathew, Ioannis Sourdis
2012 — conf
A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems.
ISED
Jamil Galadanci, Rishad A. Shafik, Jimson Mathew, Amit Acharyya, Dhiraj K. Pradhan
2012 J jnl
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits.
J. Low Power Electron.
Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2012 — conf
RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.
ISVLSI
Rishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2012 — conf
STEP: a unified design methodology for secure test and IP core protection.
ACM Great Lakes Symposium on VLSI
Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2012 J jnl
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.
Integr.
Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan
2012 C conf
The DeSyRe Project: On-Demand System Reliability.
DSD
Ioannis Sourdis, Christos Strydis, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Kim Sunesen, Stavros Tzilis
2012 — conf
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.
VDAT
Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2011 J jnl
A Routing-Aware ILS Design Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty
2011 J jnl
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electron.
Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski
2011 — conf
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields.
ECCTD
Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2011 — conf
BCH code based multiple bit error correction in finite field multiplier circuits.
ISQED
Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty
2011 J jnl
Fault Tolerant Single Error Correction Encoders.
J. Electron. Test.
Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan
2011 J jnl
Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks.
Int. J. Sens. Networks
Vishram Mishra, Jimson Mathew, Dhiraj K. Pradhan
2011 J jnl
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst.
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2011 J jnl
Matrix Codes for Reliable and Cost Efficient Memory Chips.
IEEE Trans. Very Large Scale Integr. Syst.
Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak
2011 J jnl
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN.
Circuits Syst. Signal Process.
Jimson Mathew, Koushik Maharatna, Babita R. Jose, Hafizur Rahaman, Dhiraj K. Pradhan
2011 J jnl
Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.
IEEE Trans. Reliab.
Costas Argyrides, Raul Chipana, Fabian Vargas, Dhiraj K. Pradhan
2011 — conf
Single-Event Transient Analysis in High Speed Circuits.
ISED
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
2011 — conf
Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits.
ISED
Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2011 Misc conf
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.
VLSI Design
Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski
2010 — conf
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.
ISQED
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan
2010 Misc conf
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.
VLSI Design
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan
2010 — conf
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.
ACM Great Lakes Symposium on VLSI
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan
2010 J jnl
A Galois field-based logic synthesis with testability.
IET Comput. Digit. Tech.
Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan
2010 — conf
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V
ASP-DAC
Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
2010 — conf
Clustered De Bruijn Based Multi Layered Architectures for Sensor Networks.
WiMo
Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan
2010 J jnl
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM.
J. Low Power Electron.
Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos
2010 — conf
Evaluation of a new low cost software level fault tolerance technique to cope with soft errors.
LATW
Jimmy Tarrillo, Carlos Arthur Lang Lisbôa, Luigi Carro, Costas Argyrides, Dhiraj K. Pradhan
2010 — conf
Fault diagnosis in multi layered De Bruijn based architectures for sensor networks.
PerCom Workshops
Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan
2010 — conf
Improved Yield in Nanotechnology Circuits Using Non-square Meshes.
ISVLSI
Costas Argyrides, Nikolaos Mavrogiannakis, Dhiraj K. Pradhan
2010 — conf
Improving reliability for bit parallel finite field multipliers using Decimal Hamming.
EWDTS
Nikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan
2010 J jnl
Introduction to design techniques for energy harvesting.
ACM J. Emerg. Technol. Comput. Syst.
Taskin Koçak, Dhiraj K. Pradhan
2010 A conf
Investigating the impact of NBTI on different power saving cache strategies.
DATE
Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
2010 — conf
Layout-aware Illinois Scan design for high fault coverage coverage.
ISQED
Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2010 — conf
On the design of different concurrent EDC schemes for S-Box and GF(p).
ISQED
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan
2010 C conf
On the synthesis of attack tolerant cryptographic hardware.
VLSI-SoC
Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir
2010 — conf
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.
ISQED
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan
2010 J jnl
Secure Testable S-box Architecture for Cryptographic Hardware Implementation.
Comput. J.
Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan
2010 J jnl
Simplified bit parallel systolic multipliers for special class of galois field (2
IET Comput. Digit. Tech.
Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2010 J jnl
Test Generation in Systolic Architecture for Multiplication Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan
2010 J jnl
ULS: A dual-
ACM J. Emerg. Technol. Comput. Syst.
Saraju P. Mohanty, Dhiraj K. Pradhan
2009 C conf
A fast error correction technique for matrix multiplication algorithms.
IOLTS
Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro
2009 J jnl
An O(m
Quantum Inf. Comput.
Dmitri Maslov, Jimson Mathew, Donny Cheung, Dhiraj K. Pradhan
2009 C conf
C-testable S-box implementation for secure advanced encryption standard.
IOLTS
Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2009 — conf
Increasing memory yield in future technologies through innovative design.
ISQED
Costas Argyrides, Ahmad A. Al-Yamani, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan
2009 — conf
Reliability aware yield improvement technique for nanotechnology based circuits.
SBCCI
Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro
2009 Misc conf
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
VLSI Design
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
2009 — conf
Single element correction in sorting algorithms with minimum delay overhead.
LATW
Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro
2009 A conf
Single ended 6T SRAM with isolated read-port for low-power embedded systems.
DATE
Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew
2009 J jnl
Single error correctable bit parallel multipliers over GF(2
IET Comput. Digit. Tech.
Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan
2008 Misc conf
A Galois Field Based Logic Synthesis Approach with Testability.
VLSI Design
Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan
2008 C conf
A nano-CMOS process variation induced read failure tolerant SRAM cell.
ISCAS
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
2008 J jnl
A single ended 6T SRAM cell design for ultra-low-voltage applications.
IEICE Electron. Express
Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty
2008 — conf
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
SoCC
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2008 Misc conf
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
VTS
Carlos Arthur Lang Lisbôa, Costas Argyrides, Dhiraj K. Pradhan, Luigi Carro
2008 — conf
Application of Galois Fields to Logic Synthesis.
ICIIS
Dhiraj K. Pradhan
2008 — conf
Area Reliability Trade-Off in Improved Reed Muller Coding.
SAMOS
Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan
2008 J jnl
C-testable bit parallel multipliers over
ACM Trans. Design Autom. Electr. Syst.
Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir
2008 A conf
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
DATE
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2008 J jnl
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).
IEEE Trans. Computers
Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir
2008 C conf
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.
IOLTS
Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2008 Misc conf
Design of Reversible Finite Field Arithmetic Circuits with Error Detection.
VLSI Design
Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan
2008 C conf
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement.
IOLTS
Costas Argyrides, Fabian Vargas, Marlon Moraes, Dhiraj K. Pradhan
2008 J jnl
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan
2008 — conf
Failure analysis for ultra low power nano-CMOS SRAM under process variations.
SoCC
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
2008 C conf
Fault Tolerant Reversible Finite Field Arithmetic Circuits.
IOLTS
Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan
2008 C conf
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS
Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan
2008 — ch.
Fault-Tolerant Computing.
Wiley Encyclopedia of Computer Science and Engineering
Bharat Joshi, Dhiraj K. Pradhan, Jack J. Stiffler
2008 J jnl
Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hongwei Zhu, Ilie I. Luican, Florin Balasa, Dhiraj K. Pradhan
2008 J jnl
GfXpress: A Technique for Synthesis and Optimization of GF(2
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
2008 — conf
Multiple Event Upsets Aware FPGAs Using Protected Schemes.
Fault-Tolerant Distributed Algorithms on VLSI Chips
Costas Argyrides, Dhiraj K. Pradhan
2008 — conf
On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography.
TQC
Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan
2008 — conf
Pseudo parallel architecture for AES with error correction.
SoCC
Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan
2008 J jnl
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.
IET Comput. Digit. Tech.
Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan
2008 Misc conf
Single Error Correcting Finite Field Multipliers Over GF(2m).
VLSI Design
Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan
2008 — conf
Yield improvement and power aware low cost memory chips.
WREFT@CF
Costas Argyrides, Stephania Loizidou Himona, Dhiraj K. Pradhan
2007 J jnl
A Defect Tolerance Scheme for Nanotechnology Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ahmad A. Al-Yamani, S. Ramsundar, Dhiraj K. Pradhan
2007 J jnl
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers
Abusaleh M. Jabir, Dhiraj K. Pradhan
2007 J jnl
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers
Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh
2007 — conf
A soft error robust and power aware memory design.
SBCCI
Costas Argyrides, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan
2007 — conf
A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications.
SoCC
Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan
2007 C conf
CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.
ISCAS
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
2007 C conf
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.
ISCAS
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
2007 Misc conf
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
VLSI Design
Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan
2007 — conf
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm.
ISQED
S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan
2007 C conf
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.
IOLTS
Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan
2007 A conf
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.
IPDPS
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
2007 — conf
High defect tolerant low cost memory chips.
SoCC
Costas Argyrides, Ahmad A. Al-Yamani, Dhiraj K. Pradhan
2007 C conf
Highly Reliable Power Aware Memory Design.
IOLTS
Costas Argyrides, Dhiraj K. Pradhan
2007 — conf
Improved decoding algorithm for high reliable reed muller coding.
SoCC
Costas Argyrides, Dhiraj K. Pradhan
2007 — conf
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories.
DFT
Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
2007 C conf
Multiple Upsets Tolerance in SRAM Memory.
ISCAS
Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
2007 C conf
On the Hardware Reduction of z-Datapath of Vectoring CORDIC.
ISCAS
R. Stapenhurst, Koushik Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
2007 — conf
Reliable network-on-chip based on generalized de Bruijn graph.
HLDVT
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
2007 — conf
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
ISQED
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
2007 — conf
Single Event Upset Detection and Correction.
ICIT
Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan
2007 C conf
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.
ISCAS
Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
2007 Misc conf
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).
VTS
Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan
2006 A conf
An efficient technique for synthesis and optimization of polynomials in GF(2
ICCAD
Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
2006 — conf
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m).
HLDVT
Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2006 A conf
Reuse-based test access and integrated test scheduling for network-on-chip.
DATE
Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
2006 Misc conf
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.
VTS
Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan
2005 C conf
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.
IOLTS
Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir
2005 A conf
Comparative study of CA with phase shifters and GLFSRs.
ITC
S. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan
2005 J jnl
EBIST: a novel test generator with built-in fault detection capability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dhiraj K. Pradhan, Chunsheng Liu
2005 — conf
GASIM: a fast Galois field based simulator for functional model.
HLDVT
Dhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir
2005 Misc conf
Recent Advances in Verification, Equivalence Checking and SAT-Solvers.
VLSI Design
Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea
2004 — conf
LPRAM: a low power DRAM with testability.
ASP-DAC
Subhasis Bhattacharjee, Dhiraj K. Pradhan
2004 J jnl
LPRAM: a novel low-power high-performance RAM design with testability and scalability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Subhasis Bhattacharjee, Dhiraj K. Pradhan
2004 — conf
MODD for CF: a representation for fast evaluation of multiple-output functions.
HLDVT
T. L. Rajaprabhu, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan
2004 A conf
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
DATE
Abusaleh M. Jabir, Dhiraj K. Pradhan
2004 A conf
NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances.
SAT
Sathiamoorthy Subbarayan, Dhiraj K. Pradhan
2004 — conf
NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances.
SAT (Selected Papers
Sathiamoorthy Subbarayan, Dhiraj K. Pradhan
2004 A conf
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.
ITC
Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan
2003 J jnl
A BIST Pattern Generator Design for Near-Perfect Fault Coverage.
IEEE Trans. Computers
Mitrajit Chatterjee, Dhiraj K. Pradhan
2003 A conf
EBIST: A Novel Test Generator with Built-In Fault Detection Capability.
DATE
Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty
2003 — conf
Logic transformation and coding theory-based frameworks for Boolean satisfiability.
HLDVT
Dhiraj K. Pradhan
2003 — conf
Mathematical framework for representing discrete functions as word-level polynomials.
HLDVT
Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski
2003 — conf
Wormhole routing in de Bruijn networks and hyper-de Bruijn networks.
ISCAS (3)
Elango Ganesan, Dhiraj K. Pradhan
2001 Misc conf
ATPG for Design Errors-Is It Possible?
VTS
Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
2001 — conf
Logic Insertion to Speed-Up Logic Verification: A Recent Development.
IOLTW
Dhiraj K. Pradhan
2000 J jnl
Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers
Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan
2000 J jnl
VERILAT: verification using logic augmentation and transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan
1999 J jnl
GLFSR-a new test pattern generator for built-in-self-test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dhiraj K. Pradhan, Mitrajit Chatterjee
1998 J jnl
Job Scheduling in Mesh Multicomputers.
IEEE Trans. Parallel Distributed Syst.
Debendra Das Sharma, Dhiraj K. Pradhan
1998 J jnl
LOT: Logic Optimization with Testability. New transformations for logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
1997 J jnl
A cluster-based approach for routing in dynamic networks.
Comput. Commun. Rev.
P. Krishna, Nitin H. Vaidya, Mainak Chatterjee, Dhiraj K. Pradhan
1997 A conf
Improving Performance of TCP over Wireless Networks.
ICDCS
Bikram S. Bakshi, P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
1997 J jnl
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off.
IEEE Trans. Computers
Dhiraj K. Pradhan, Nitin H. Vaidya
1996 J jnl
A novel framework for logic verification in a synthesis environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy
1996 — conf
BIT-based weighted mean filter.
EUSIPCO
Barun K. Kar, Mitrajit Chatterjee, Dhiraj K. Pradhan
1996 A conf
Gate-level synthesis for low-power using new transformations.
ISLPED
Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
1996 J jnl
Modified tree structure for location management in mobile environments.
Comput. Commun.
Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch
1996 B conf
Providing Seamless Communication in Mobile Wireless Networks.
LCN
Bikram S. Bakshi, P. Krishna, Dhiraj K. Pradhan, Nitin H. Vaidya
1996 — conf
Recoverable Mobile Environment: Design and Trade-Off Analysis.
FTCS
Dhiraj K. Pradhan, P. Krishna, Nitin H. Vaidya
1996 A conf
Sequential redundancy identification using recursive learning.
ICCAD
Wanlin Cao, Dhiraj K. Pradhan
1996 J jnl
Static and adaptive location management in mobile wireless networks.
Comput. Commun.
P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
1996 J jnl
Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability.
J. Parallel Distributed Comput.
Debendra Das Sharma, Dhiraj K. Pradhan
1996 J jnl
Synthesis of initializable asynchronous circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
1996 J jnl
The Effect of Program Behavior on Fault Observability.
IEEE Trans. Computers
Nicholas S. Bowen, Dhiraj K. Pradhan
1996 J jnl
Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa.
IEEE Trans. Computers
Sandeep K. Gupta, Dhiraj K. Pradhan
1996 A conf
VERILAT: verification using logic augmentation and transformations.
ICCAD
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee
1995 — conf
A Cluster-based Approach for Routing in Ad-Hoc Networks.
Symposium on Mobile and Location-Independent Computing
P. Krishna, Mainak Chatterjee, Nitin H. Vaidya, Dhiraj K. Pradhan
1995 J jnl
A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms.
IEEE Trans. Computers
Nicholas S. Bowen, Dhiraj K. Pradhan
1995 Misc conf
A novel pattern generator for near-perfect fault-coverage.
VTS
Mitrajit Chatterjee, Dhiraj K. Pradhan
1995 J jnl
A novel scheme to reduce test application time in circuits with full scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dhiraj K. Pradhan, Jayashree Saxena
1995 J jnl
Fault Injection: A Method for Validating Computer-System Dependability.
Computer
Jeffrey A. Clark, Dhiraj K. Pradhan
1995 A conf
LOT: logic optimization with testability-new transformations using recursive learning.
ICCAD
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
1995 A* conf
Modified Tree Structure for Location Management in Mobile Environments.
INFOCOM
Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch
1995 A* conf
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
DAC
Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan
1995 J jnl
Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation.
IEEE Trans. Parallel Distributed Syst.
Debendra Das Sharma, Dhiraj K. Pradhan
1994 C conf
Bit-Serial Generalized Median Filters.
ISCAS
Barun K. Kar, Khadem M. Yusuf, Dhiraj K. Pradhan
1994 Misc conf
Functional learning: a new approach to learning in digital circuits.
VTS
Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan
1994 A conf
GLFSR - A New Test Pattern Generator for Built-In Self-Test.
ITC
Dhiraj K. Pradhan, Mitrajit Chatterjee
1994 C conf
Initialization Isuues in the Synthesis of Asynchronous Circuits.
ICCD
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
1994 — conf
Job Scheduling in Mesh Multicomputers.
ICPP (2)
Debendra Das Sharma, Dhiraj K. Pradhan
1994 — conf
Location Management in Distributed Mobile Environments.
PDIS
P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
1994 — conf
Recovery in Multicomputers with Finite Error Detection Latency.
ICPP (2)
P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan
1994 J jnl
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dhiraj K. Pradhan
1994 J jnl
Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture.
IEEE Trans. Computers
Dhiraj K. Pradhan, Nitin H. Vaidya
1994 — conf
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off.
FTCS
Dhiraj K. Pradhan, Nitin H. Vaidya
1994 J jnl
Safe System Level Diagnosis.
IEEE Trans. Computers
Nitin H. Vaidya, Dhiraj K. Pradhan
1994 — conf
Signal Transition Graph Transformations for Initializability.
EDAC-ETC-EUROASIC
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
1994 — conf
Subcube Level Time-Sharing in Hypercube Multicomputers.
ICPP (2)
Debendra Das Sharma, G. D. Holland, Dhiraj K. Pradhan
1994 Misc conf
Synthesis of Initializable Asynchronous Circuits.
VLSI Design
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
1993 — conf
A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers.
SPDP
Debendra Das Sharma, Dhiraj K. Pradhan
1993 A conf
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits.
ITC
Jayashree Saxena, Dhiraj K. Pradhan
1993 J jnl
A new algorithm for order statistic and sorting.
IEEE Trans. Signal Process.
Barun K. Kar, Dhiraj K. Pradhan
1993 J jnl
Accelerated dynamic learning for test pattern generation in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wolfgang Kunz, Dhiraj K. Pradhan
1993 — conf
An application specific processor for implementing stack filters.
ASAP
Barun K. Kar, R. C. K. Kumar, Dhiraj K. Pradhan
1993 A conf
Buffer assignment for data driven architectures.
ICCAD
Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
1993 J jnl
Communication structures in fault-tolerant distributed systems.
Networks
Dhiraj K. Pradhan, Fred J. Meyer
1993 A conf
Degradable Agreement in the Presence of Byzantine Faults.
ICDCS
Nitin H. Vaidya, Dhiraj K. Pradhan
1993 C conf
Desgin for Testability of Asynchronous Sequential Circuits.
ICCD
Jayashree Saxena, Dhiraj K. Pradhan
1993 — conf
Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors.
ICPP (1)
Debendra Das Sharma, Dhiraj K. Pradhan
1993 J jnl
Fault-Tolerant Design Strategies for High Reliability and Safety.
IEEE Trans. Computers
Nitin H. Vaidya, Dhiraj K. Pradhan
1993 J jnl
Modeling Live and Dead Lines in Cache Memory Systems.
IEEE Trans. Computers
Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan
1993 — conf
Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks.
IPPS
Elango Ganesan, Dhiraj K. Pradhan
1993 J jnl
Processor- and Memory-Based Checkpoint and Rollback Recovery.
Computer
Nicholas S. Bowen, Dhiraj K. Pradhan
1993 — conf
Roll-Forward Checkpointing Schemes.
Hardware and Software Architectures for Fault Tolerance
Dhiraj K. Pradhan, Debendra Das Sharma, Nitin H. Vaidya
1993 — conf
Scalability of Binary deBruijn Networks.
SPDP
Barun K. Kar, Dhiraj K. Pradhan
1993 J jnl
The Hyper-deBruijn Networks: Scalable Versatile Architecture.
IEEE Trans. Parallel Distributed Syst.
Elango Ganesan, Dhiraj K. Pradhan
1993 J jnl
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
IEEE Trans. Very Large Scale Integr. Syst.
D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan
1992 — conf
A Hierarchical Directory Scheme for Large-Scale Cache-Coherent Multipmcessors.
IPPS
Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut
1992 — conf
A Novel Approach for Subcube Allocation in Hypercube Multiprocessors.
SPDP
Debendra Das Sharma, Dhiraj K. Pradhan
1992 Misc conf
A design for testability scheme to reduce test application time in full scan.
VTS
Dhiraj K. Pradhan, Jayashree Saxena
1992 J jnl
A new class of bit- and byte-error control codes.
IEEE Trans. Inf. Theory
Nitin H. Vaidya, Dhiraj K. Pradhan
1992 A conf
Can Concurrent Checkers Help BIST?
ITC
Sandeep K. Gupta, Dhiraj K. Pradhan
1992 A conf
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits.
ITC
Wolfgang Kunz, Dhiraj K. Pradhan
1992 J jnl
Virtual Checkpoints: Architecture and Performance.
IEEE Trans. Computers
Nicholas S. Bowen, Dhiraj K. Pradhan
1991 J jnl
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sandeep K. Gupta
1991 A conf
A virtual memory translation mechanism to support checkpoint and rollback recovery.
SC
Nicholas S. Bowen, Dhiraj K. Pradhan
1991 A conf
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model.
ITC
Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan
1991 — conf
BDG-torus union graph-an efficient algorithmically specializedparallel interconnect.
SPDP
Neeraj Suri, Avi Mendelson, Dhiraj K. Pradhan
1991 J jnl
Consensus With Dual Failure Modes.
IEEE Trans. Parallel Distributed Syst.
Fred J. Meyer, Dhiraj K. Pradhan
1991 — conf
Program Fault Tolerance Based on Memory Access Behavior.
FTCS
Nicholas S. Bowen, Dhiraj K. Pradhan
1991 — conf
System Level Diagnosis: Combining Detection and Location.
FTCS
Nitin H. Vaidya, Dhiraj K. Pradhan
1991 A conf
The hyper-deBruijn multiprocessor networks.
ICDCS
Elango Ganesan, Dhiraj K. Pradhan
1991 J jnl
Two economical directory schemes for large-scale cache coherent multiprocessors.
SIGARCH Comput. Archit. News
Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut
1991 J jnl
Yield optimization in large RAM's with hierarchical redundancy.
IEEE J. Solid State Circuits
Kumar N. Ganapathy, Adit D. Singh, Dhiraj K. Pradhan
1990 J jnl
Aliasing Probability for Multiple Input Signature Analyzer.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky
1990 — conf
Application specific VLSI architectures based on De Bruijn graphs.
ASAP
Dhiraj K. Pradhan
1990 J jnl
Design and Analysis of a Gracefully Degrading Interleaved Memory System.
IEEE Trans. Computers
Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
1990 J jnl
Error-Control Coding in Computers.
Computer
Eiji Fujiwara, Dhiraj K. Pradhan
1990 — conf
Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems.
ICPP (1)
Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan
1990 — conf
Zero aliasing compression.
FTCS
Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy
1989 J jnl
A single cached copy data coherence scheme for multiprocessor systems.
SIGARCH Comput. Archit. News
Abraham Mendelson, Dhiraj K. Pradhan, Adit D. Singh
1989 J jnl
Dynamic Testing Strategy for Distributed Systems.
IEEE Trans. Computers
Fred J. Meyer, Dhiraj K. Pradhan
1989 — conf
Fault-Tolerant VLSI Architectures Based on de Bruijn Graphs (Galileo in the Mid Nineties).
Reliability Of Computer And Communication Networks
Dhiraj K. Pradhan
1989 J jnl
Modeling Defect Spatial Distribution.
IEEE Trans. Computers
Fred J. Meyer, Dhiraj K. Pradhan
1989 J jnl
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI.
IEEE Trans. Computers
Maheswara R. Samatham, Dhiraj K. Pradhan
1988 A conf
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability.
ITC
Sandeep K. Gupta, Dhiraj K. Pradhan
1988 J jnl
Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay.
IEEE J. Solid State Circuits
Israel Koren, Zahava Koren, Dhiraj K. Pradhan
1988 J jnl
Flip-Trees: Fault-Tolerant Graphs with Wide Containers.
IEEE Trans. Computers
Fred J. Meyer, Dhiraj K. Pradhan
1988 A conf
RTRAM: Reconfigurable and Testable Multi-Bit RAM Design.
ITC
Dhiraj K. Pradhan, Nirmala R. Kamath
1988 J jnl
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
IEEE Trans. Computers
Najmi T. Jarwala, Dhiraj K. Pradhan
1987 J jnl
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems.
IEEE Trans. Computers
Israel Koren, Dhiraj K. Pradhan
1987 A* conf
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
ISCA
Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
1986 J jnl
Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems.
Proc. IEEE
Israel Koren, Dhiraj K. Pradhan
1985 J jnl
Dynamically Restructurable Fault-Tolerant Processor Network Architectures.
IEEE Trans. Computers
Dhiraj K. Pradhan
1985 J jnl
Fault-Tolerant Multiprocessor Link and Bus Network Architectures.
IEEE Trans. Computers
Dhiraj K. Pradhan
1985 A* conf
The de Bruijn Multiprocessor Network: A Versatile Sorting Network.
ISCA
Maheswara R. Samatham, Dhiraj K. Pradhan
1984 A* conf
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation.
ISCA
Maheswara R. Samatham, Dhiraj K. Pradhan
1983 J jnl
Sequential Network Design Using Extra Inputs for Fault Detection.
IEEE Trans. Computers
Dhiraj K. Pradhan
1982 J jnl
A Fault-Tolerant Communication Architecture for Distributed Systems.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sudhakar M. Reddy
1982 A conf
On a Class of Fault-Tolerant Multiprocessor Network Architectures.
ICDCS
Dhiraj K. Pradhan
1982 J jnl
Optimal Unidirectional Error Detecting/Correcting Codes.
IEEE Trans. Computers
Bella Bose, Dhiraj K. Pradhan
1981 A conf
Completely Self-Checking Checkers in PLAs.
ITC
Kyushik Son, Dhiraj K. Pradhan
1980 J jnl
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications.
IEEE Trans. Computers
Dhiraj K. Pradhan
1980 J jnl
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines.
IEEE Trans. Computers
Dhiraj K. Pradhan, Kolar L. Kodandapani
1980 J jnl
Error-Correcting Codes and Self-Checking Circuits.
Computer
Dhiraj K. Pradhan, Jack J. Stiffler
1980 J jnl
Fault-Tolerant Computing.
Computer
Dhiraj K. Pradhan
1980 J jnl
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets.
IEEE Trans. Computers
Kolar L. Kodandapani, Dhiraj K. Pradhan
1978 J jnl
A Theory of Galois Switching Functions.
IEEE Trans. Computers
Dhiraj K. Pradhan
1978 J jnl
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design.
IEEE Trans. Computers
Dhiraj K. Pradhan
1978 J jnl
Fault-Tolerant Asynchronous Networks Using Read-Only Memories.
IEEE Trans. Computers
Dhiraj K. Pradhan
1978 J jnl
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays.
IEEE Trans. Computers
Dhiraj K. Pradhan
1977 J jnl
A graph-structural approach for the generalization of data management systems.
Inf. Sci.
L. C. Chang, Dhiraj K. Pradhan
1977 J jnl
Store Address Generator with On-Line Fault-Detection Capability.
IEEE Trans. Computers
M. Y. Hsiao, Arvind M. Patel, Dhiraj K. Pradhan
1976 J jnl
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sudhakar M. Reddy
1975 J jnl
Reed-Muller Like Canonic Forms for Multivalued Functions.
IEEE Trans. Computers
Dhiraj K. Pradhan, Arvind M. Patel
1974 J jnl
Design of Two-Level Fault-Tolerant Networks.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sudhakar M. Reddy
1974 J jnl
Fault-Tolerant Carry-Save Adders.
IEEE Trans. Computers
Dhiraj K. Pradhan
1973 J jnl
Fault-Tolerant Asynchronous Networks.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sudhakar M. Reddy
1972 J jnl
Error-Control Techniques for Logic Processors.
IEEE Trans. Computers
Dhiraj K. Pradhan, Sudhakar M. Reddy