Dhamin Al-Khalili

66 papers A* 1A 4C 7Misc 2Journal 26Unranked 26

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations. ISCAS Waqas Gul, Maitham Shams, Dhamin Al-Khalili
2018	J	`jnl`	Gate Oxide Short Defect Model in FinFETs. J. Electron. Test. Roya Dibaj, Dhamin Al-Khalili, Maitham Shams
2017	Misc	`conf`	Comprehensive investigation of gate oxide short in FinFETs. VTS Roya Dibaj, Dhamin Al-Khalili, Maitham Shams
2017	—	`conf`	Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. CCECE Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
2017	J	`jnl`	Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput. Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
2013	J	`jnl`	Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs. J. Electr. Comput. Eng. Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon
2012	—	`conf`	An improved BCD adder using 6-LUT FPGAs. NEWCAS Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2012	J	`jnl`	Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Comput. Digit. Tech. Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois
2012	—	`conf`	Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs. NEWCAS Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon
2011	—	`conf`	A CNFET-based characterization framework for digital circuits. ICECS Jacques Laurent Athow, Côme Rozon, Dhamin Al-Khalili, J. M. Pierre Langlois
2011	—	`conf`	Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2011	—	`conf`	Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2011	—	`conf`	Cell stack length using an enhanced logical effort model for a library-free paradigm. ICECS Hisham El-Masry, Dhamin Al-Khalili
2010	J	`jnl`	FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. J. Signal Process. Syst. Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2010	—	`conf`	Pattern-Driven Clock Tree Routing with Via Minimization. ISVLSI Ali M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili
2009	J	`jnl`	Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfigurable Comput. Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2009	—	`conf`	Two level decomposition based matrix multiplication for FPGAs. ICECS Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2008	C	`conf`	Efficient FPGA implementation of complex multipliers using the logarithmic number system. ISCAS Man Yan Kong, J. M. Pierre Langlois, Dhamin Al-Khalili
2008	J	`jnl`	UDSM subthreshold leakage model for NMOS transistor stacks. Microelectron. J. Hussam Al-Hertani, Dhamin Al-Khalili, Côme Rozon
2007	—	`conf`	FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2007	J	`jnl`	Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Comput. Digit. Tech. Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2006	C	`conf`	Accurate Total Static Leakage Current Estimation in Transistor Stacks. AICCSA Hussam Al-Hertani, Dhamin Al-Khalili, Côme Rozon
2006	C	`conf`	An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2006	J	`jnl`	Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. Integr. Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon
2006	J	`jnl`	Carry-free approximate squaring functions with O(n) complexity and O(1) delay. IEEE Trans. Circuits Syst. II Express Briefs J. M. Pierre Langlois, Dhamin Al-Khalili
2006	—	`conf`	Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois
2005	J	`jnl`	Delay analysis of CMOS gates using modified logical effort model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
2005	—	`conf`	Leakage power dissipation in UDSM logic gates. Circuits, Signals, and Systems Hussam Al-Hertani, Dhamin Al-Khalili, Côme Rozon
2005	J	`jnl`	Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
2004	—	`conf`	Clock tree tuning using shortest paths polygon. SoCC Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili
2003	—	`conf`	Adaptive wire adjustment for bounded skew Clock Distribution Network. ASP-DAC Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
2003	J	`jnl`	IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs. IEEE Trans. Computers Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon
2003	—	`conf`	Low power direct digital frequency synthesizers in 0.18 μm CMOS. CICC J. M. Pierre Langlois, Dhamin Al-Khalili
2003	J	`jnl`	Novel approach to the design of direct digital frequency synthesizers based on linear interpolation. IEEE Trans. Circuits Syst. II Express Briefs J. M. Pierre Langlois, Dhamin Al-Khalili
2003	J	`jnl`	Technology-portable analytical model for DSM CMOS inverter transition-time estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
2002	—	`conf`	A low power direct digital frequency synthesizer with 60 dBc spectral purity. ACM Great Lakes Symposium on VLSI J. M. Pierre Langlois, Dhamin Al-Khalili
2002	J	`jnl`	Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models. Integr. Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon
2002	—	`conf`	Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. ISCAS (5) J. M. Pierre Langlois, Dhamin Al-Khalili
2002	J	`jnl`	Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation. J. VLSI Signal Process. J. M. Pierre Langlois, Dhamin Al-Khalili, Robert J. Inkol
2002	—	`conf`	Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. Timing Issues in the Specification and Synthesis of Digital Systems Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
2001	J	`jnl`	A Low Power Approach to Floating Point Adder Design for DSP Applications. J. VLSI Signal Process. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah
2001	A	`conf`	Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. ICCAD Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon
2001	—	`conf`	Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. ISCAS (5) Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon
2001	—	`conf`	Low power floating point MAFs-a comparative study. ISSPA R. V. K. Pillai, S. Y. A. Shah, A. J. Al-Khalili, Dhamin Al-Khalili
2000	—	`conf`	A CAD tool for first hand CMOS circuit selection. ICECS P. Sun, A. J. Al-Khalili, Dhamin Al-Khalili
2000	—	`conf`	Behavioural synthesis of low power floating point CORDIC processors. ICECS Joe Costello, Dhamin Al-Khalili
2000	—	`conf`	Comparing defect coverage for current-mode logic and CMOS VLSI cells. ICECS Côme Rozon, Dhamin Al-Khalili, Saman Adham, Douglas Racz
2000	C	`conf`	Comprehensive defect analysis and testability of current-mode logic circuits. ISCAS Saman Adham, Dhamin Al-Khalili, Côme Rozon, Douglas Racz
1999	—	`conf`	An IEEE Compliant Floating Point MAF. VLSI R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
1999	—	`conf`	Power implications of precision limited arithmetic in floating point FIR filters. ISCAS (1) R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
1999	J	`jnl`	Synthesis of low-power CMOS circuits using hybrid topologies. Integr. Michael Gallant, Dhamin Al-Khalili
1998	Misc	`conf`	A Low Power Floating Point Accumulator. VLSI Design R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili
1998	—	`conf`	Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. DFT Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz
1998	A	`conf`	VHDL Modelling and Analysis of Fault Secure Systems. DATE Jason Coppens, Dhamin Al-Khalili, Côme Rozon
1997	C	`conf`	A Low Power Approach to Floating Point Adder Design. ICCD R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
1997	A	`conf`	Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. ISLPED R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
1996	A	`conf`	Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ISLPED R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
1995	J	`jnl`	Design techniques for fault-tolerant systolic arrays. J. VLSI Signal Process. Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili
1994	J	`jnl`	A floating-point systolic array processing element with serial communication and built-in self-test. J. VLSI Signal Process. T. C. Davies, Dhamin Al-Khalili, Valek Szwarc
1994	J	`jnl`	Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. VLSI Design Michael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon
1993	C	`conf`	Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. ISCAS Michael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon
1992	J	`jnl`	Testability analysis and fault modeling of BiCMOS circuits. J. Electron. Test. Dhamin Al-Khalili, Côme Rozon, B. Stewart
1990	J	`jnl`	A module generator for optimized CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
1989	A*	`conf`	A Module Generator for Optimized CMOS Buffers. DAC Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
1988	J	`jnl`	An algorithm for polygon conversion to boxes for VLSI layouts. Integr. Asim J. Al-Khalili, Dhamin Al-Khalili, Khaled Ammar
1981	J	`jnl`	Measuring the instability of AC arc discharges. Microprocess. Microsystems Mazin Kadhim, Dhamin Al-Khalili, Imaddin Al-Bazz