Devesh Dwivedi

14 papers Misc 1Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2023 Misc conf
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process.
VLSID
Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi
2023 — conf
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications.
APCCAS
Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu
2021 J jnl
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications.
Integr.
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi
2020 J jnl
Design of Approximate Booth Squarer for Error-Tolerant Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi
2019 J jnl
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM.
Circuits Syst. Signal Process.
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi
2018 — conf
Design of Approximate Dividers for Error Tolerant Applications.
MWSCAS
Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi
2016 J jnl
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations.
Microelectron. J.
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
2016 — conf
A robust 8T FinFET SRAM cell with improved stability for low voltage applications.
VDAT
C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan
2016 J jnl
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.
Circuits Syst. Signal Process.
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
2016 J jnl
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance.
Circuits Syst. Signal Process.
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi
2015 — conf
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I
ACM Great Lakes Symposium on VLSI
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi
2015 — conf
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity.
iNIS
Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi
2014 — conf
Single-ended sub-threshold finfet 7T SRAM cell without boosted supply.
ICICDT
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
2012 — conf
Voltage up level shifter with improved performance and reduced power.
CCECE
Devesh Dwivedi, Suman Dwivedi, Eswararao Potladhurthi