Deshanand P. Singh

35 papers A* 3A 10B 5C 1Journal 7Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	A*	`conf`	Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. DAC Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah
2024	J	`jnl`	Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. CoRR Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah
2024	—	`conf`	PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. CF Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna
2024	J	`jnl`	Primate: A Framework to Automatically Generate Soft Processors for Network Applications. IEEE Comput. Archit. Lett. Rui Ma, Jia-Ching Hsu, Ali Mansoorshahi, Joseph Garvey, Michael Kinsner, Deshanand P. Singh, Derek Chiou
2023	J	`jnl`	A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. CoRR Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna
2016	—	`ch.`	OpenCL. FPGAs for Software Programmers Deshanand P. Singh, Peter Yiannacouras
2015	A	`conf`	High-Level Design Tools for Floating Point FPGAs. FPGA Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski
2014	—	`conf`	Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL. IWOCL Mohamed S. Abdelfattah, Andrei Hagiescu, Deshanand P. Singh
2013	—	`conf`	Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. ASP-DAC Doris Chen, Deshanand P. Singh
2013	A	`conf`	Harnessing the power of FPGAs using altera's OpenCL compiler. FPGA Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling
2013	J	`jnl`	Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications. ACM Trans. Archit. Code Optim. Doris Chen, Deshanand P. Singh
2012	B	`conf`	From opencl to high-performance hardware on FPGAS. FPL Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh
2012	B	`conf`	Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. FPL Doris Chen, Deshanand P. Singh
2011	A	`conf`	Line-level incremental resynthesis techniques for FPGAs. FPGA Doris Chen, Deshanand P. Singh
2010	A	`conf`	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz
2010	B	`conf`	Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs). FPL Doris Chen, Deshanand P. Singh
2007	J	`jnl`	An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. Deshanand P. Singh, Stephen Dean Brown
2007	J	`jnl`	FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2007	C	`conf`	Incremental placement for structured ASICs using the transportation problem. VLSI-SoC Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2007	J	`jnl`	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	—	`conf`	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	A	`conf`	Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2005	A	`conf`	FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	B	`conf`	FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	A*	`conf`	FPGA technology mapping: a study of optimality. DAC Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	A*	`conf`	Incremental retiming for FPGA physical synthesis. DAC Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2005	B	`conf`	Post-Placement BDD-Based Decomposition for FPGAs. FPL Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
2005	—	`conf`	Two-stage physical synthesis for FPGAs. CICC Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2004	—	`conf`	The Quartus University Interface Program: enabling advanced FPGA research. FPT Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown
2003	—	`conf`	An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI Deshanand P. Singh, Stephen Dean Brown
2003	—	`conf`	Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown
2002	A	`conf`	Constrained clock shifting for field programmable gate arrays. FPGA Deshanand P. Singh, Stephen Dean Brown
2002	A	`conf`	Incremental placement for layout driven optimizations on FPGAs. ICCAD Deshanand P. Singh, Stephen Dean Brown
2002	A	`conf`	Integrated retiming and placement for field programmable gate arrays. FPGA Deshanand P. Singh, Stephen Dean Brown
2001	A	`conf`	The case for registered routing switches in field programmable gate arrays. FPGA Deshanand P. Singh, Stephen Dean Brown