Deokjin Joo

11 papers A* 2Journal 7Unranked 2
YearRankTypeTitle / Venue / Authors
2017 J jnl
Clock buffer polarity assignment under useful skew constraints.
Integr.
Deokjin Joo, Taewhan Kim
2017 J jnl
Kapre: On-GPU Audio Preprocessing Layers for a Quick Implementation of Deep Neural Network Models with Keras.
CoRR
Keunwoo Choi, Deokjin Joo, Juho Kim
2016 — conf
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction.
ASP-DAC
Deokjin Joo, Taewhan Kim
2016 J jnl
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes.
Integr.
Juyeon Kim, Deokjin Joo, Taewhan Kim
2014 J jnl
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Deokjin Joo, Taewhan Kim
2013 J jnl
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim
2013 A* conf
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem.
DAC
Juyeon Kim, Deokjin Joo, Taewhan Kim
2012 J jnl
Design Methodologies for Reliable Clock Networks.
J. Comput. Sci. Eng.
Deokjin Joo, Minseok Kang, Taewhan Kim
2011 J jnl
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hochang Jang, Deokjin Joo, Taewhan Kim
2011 — conf
Clock design techniques considering circuit reliability.
ISOCC
Yonghwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim
2011 A* conf
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing.
DAC
Deokjin Joo, Taewhan Kim