Deog-Kyoon Jeong

224 papers A* 2A 3B 1C 16Journal 128Unranked 74
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 48-Gb/s PAM-4 Transceiver With Transition Boosting and RLM Calibration for Next-Generation Memory Interface Testing.
IEEE Trans. Very Large Scale Integr. Syst.
Chan-Ho Kye, Daeho Yun, Jeonghyeon Han, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong, Jooyeol Rhee
2025 J jnl
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology.
IEEE J. Solid State Circuits
Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo
2025 — conf
A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation.
CICC
Hyun-Seok Choi, Sunki Cho, Sanghee Lee, Hyeri Roh, Jeongeun Song, Honggyoo Ahn, Jihee Kim, Minchang Kim, Hankyu Chi, Deog-Kyoon Jeong, Woo-Seok Choi
2025 J jnl
A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL.
IEEE Trans. Very Large Scale Integr. Syst.
Kyungmin Baek, Jiho Kim, Kahyun Kim, Deog-Kyoon Jeong, Min-Seong Choo
2024 — conf
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology.
A-SSCC
Hong-Seok Choi, Jae-Geon Lee, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Min-Seong Choo
2024 J jnl
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Minkyo Shim, Seungha Roh, Yunhee Lee, Jung-Woo Sull, Deog-Kyoon Jeong, Kwanseo Park
2024 J jnl
A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seungha Roh, Minkyo Shim, Yoojin Jung, Deog-Kyoon Jeong, Kwanseo Park
2023 J jnl
A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Sanghee Lee, Byungjun Kang, Woogeun Rhee, Deog-Kyoon Jeong
2023 J jnl
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift.
IEEE Trans. Circuits Syst. II Express Briefs
Kwang-Hoon Lee, Jung-Hun Park, Yongjae Lee, Yeonggeun Song, Seungha Roh, Minkyo Shim, Yoonho Song, Woosong Jung, Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong
2023 — conf
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.
CICC
Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong
2023 J jnl
A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation.
IEEE Trans. Circuits Syst. II Express Briefs
Minkyo Shim, Kwang-Hoon Lee, Seungha Roh, Kwanseo Park, Deog-Kyoon Jeong
2023 J jnl
A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link.
IEEE Access
Minkyo Shim, Woonghee Lee, Yunhee Lee, Kwanseo Park, Deog-Kyoon Jeong
2023 C conf
A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector.
ISCAS
Woosong Jung, Minkyo Shim, Seungha Roh, Deog-Kyoon Jeong
2023 — conf
A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS.
ISSCC
Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong
2023 J jnl
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS.
IEEE J. Solid State Circuits
Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2023 C conf
A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation.
ISCAS
Kahyun Kim, Daeho Yun, Kyungmin Baek, Woo-Seok Choi, Deog-Kyoon Jeong
2023 — conf
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge.
A-SSCC
Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong
2023 — conf
An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS.
MWSCAS
Jung-Woo Sull, Minkyo Shim, Jung-Hun Park, Sanghee Lee, Deog-Kyoon Jeong
2023 J jnl
An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver With Hybrid Adaptation Scheme.
IEEE Trans. Circuits Syst. II Express Briefs
Yunhee Lee, Minkyo Shim, Seungha Roh, Woonghee Lee, Deog-Kyoon Jeong
2023 J jnl
An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Young-Ha Hwang, Jun Wang, Deog-Kyoon Jeong, Jun-Eun Park
2023 J jnl
An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector.
IEEE J. Solid State Circuits
Jonghyun Oh, Young-Ha Hwang, Jun-Eun Park, Mingoo Seok, Deog-Kyoon Jeong
2022 — conf
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link.
VLSI Technology and Circuits
Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
2022 — conf
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration.
ESSCIRC
Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong
2022 J jnl
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO.
IEEE Trans. Circuits Syst. II Express Briefs
Yeonggeun Song, Han-Gon Ko, Changhyun Kim, Deog-Kyoon Jeong
2022 — conf
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration.
ISSCC
Hyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog-Kyoon Jeong
2022 J jnl
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong
2022 J jnl
A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing.
IEEE Trans. Circuits Syst. II Express Briefs
Daeho Yun, Eonhui Lee, Woosong Jung, Kahyun Kim, Kyung-Min Beak, Jihee Kim, Hyun Bae Lee, Byeongseon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
2022 — conf
A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE.
ISOCC
Kyungmin Baek, Kahyun Kim, Deog-Kyoon Jeong
2022 J jnl
A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Seungha Roh, Kwangho Lee, Minkyo Shim, Moon-Chul Choi, Deog-Kyoon Jeong
2022 — conf
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller.
VLSI Technology and Circuits
Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong
2022 J jnl
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.
IEEE Trans. Circuits Syst. II Express Briefs
Soyeong Shin, Yongjae Lee, Jiheon Park, Jihyo Kang, Kyunghoon Kim, Dae-Han Kwon, Sangkwon Lee, Jieun Jang, Joo-Hwan Cho, Deog-Kyoon Jeong
2022 J jnl
A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques.
IEEE Trans. Very Large Scale Integr. Syst.
Young-Ha Hwang, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong
2022 J jnl
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation.
IEEE J. Solid State Circuits
Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong
2022 J jnl
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns.
IEEE J. Solid State Circuits
Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park
2022 J jnl
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jung-Woo Sull, Soyeong Shin, Jonghyun Oh, Kwang-Hoon Lee, Jihee Kim, Jung-Hun Park, Deog-Kyoon Jeong
2022 J jnl
Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link.
IEEE Trans. Circuits Syst. II Express Briefs
Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
2022 J jnl
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.
IEEE J. Solid State Circuits
Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
2022 J jnl
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector.
IEEE J. Solid State Circuits
Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong
2022 — conf
Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy Applications.
ISOCC
Yoonho Song, Eunseo Kim, Deog-Kyoon Jeong
2021 — conf
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link.
ESSCIRC
Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, Han-Gon Ko, Woo-Seok Choi, Deog-Kyoon Jeong
2021 J jnl
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop.
IEEE Trans. Circuits Syst. II Express Briefs
Chang-Soo Yoon, Han-Gon Ko, Byung-Jun Kang, Jung-Woo Sull, Deog-Kyoon Jeong
2021 J jnl
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access
Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
2021 J jnl
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS.
IEEE J. Solid State Circuits
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2021 — conf
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS.
A-SSCC
Kwangho Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2021 — conf
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS.
A-SSCC
Haram Ju, Kwangho Lee, Woosong Jung, Deog-Kyoon Jeong
2021 — conf
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS.
A-SSCC
Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon Jeong
2021 — conf
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS.
ISOCC
Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jung-Hoon Park, Kwanghoon Lee, Young-Ha Hwang, Deog-Kyoon Jeong
2021 — conf
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS.
ISOCC
Seungha Roh, Moon-Chul Choi, Deog-Kyoon Jeong
2021 J jnl
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.
IEEE J. Solid State Circuits
Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong
2021 — conf
A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver.
ISOCC
Yunhee Lee, Woonghee Lee, Minkyo Shim, Deog-Kyoon Jeong
2021 — conf
A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling.
ISOCC
Minkyo Shim, Woonghee Lee, Yunhee Lee, Deog-Kyoon Jeong
2021 J jnl
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong
2021 — conf
Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver.
ISOCC
Daeho Yun, Deog-Kyoon Jeong
2020 — conf
18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor.
ISSCC
Minho Choi, Deog-Kyoon Jeong
2020 — conf
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface.
ISSCC
Soyeong Shin, Han-Gon Ko, Sungchun Jang, Dongkyun Kim, Deog-Kyoon Jeong
2020 — conf
25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm
ISSCC
Jonghyun Oh, Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong
2020 — conf
32.4 A 0.4-to-1.2V 0.0057mm
ISSCC
Jun-Eun Park, Jeongho Hwang, Jonghyun Oh, Deog-Kyoon Jeong
2020 — conf
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS.
ISSCC
Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong
2020 — conf
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels.
ISSCC
Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong
2020 A* conf
A
HPCA
Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong
2020 J jnl
A
CoRR
Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong
2020 J jnl
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference.
IEEE J. Solid State Circuits
Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong
2020 — conf
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
VLSI Circuits
Moon-Chul Choi, Han-Gon Ko, Jonghyun Oh, Hye-Yoon Joo, Kwangho Lee, Deog-Kyoon Jeong
2020 J jnl
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong
2020 J jnl
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Sangyoon Lee, Han-Gon Ko, Joo-Hyung Chae, Soyeong Shin, Jaekwang Yun, Deog-Kyoon Jeong, Suhwan Kim
2020 — conf
A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS.
ISOCC
Jung-Woo Sull, Hyungrok Do, Deog-Kyoon Jeong
2020 J jnl
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Chan-Ho Kye, Han-Gon Ko, Jinhyung Lee, Deog-Kyoon Jeong
2020 J jnl
A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Hyungrok Do, Jeongho Hwang, Hong-Seok Choi, Deog-Kyoon Jeong
2020 — conf
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface.
ISOCC
Woosong Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, Deog-Kyoon Jeong
2020 J jnl
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage.
IEEE J. Solid State Circuits
Jungmin Yoon, Hyungrok Do, Daehyun Koh, Seunghan Oak, Junphyo Lee, Deog-Kyoon Jeong
2020 J jnl
A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme.
IEEE Trans. Circuits Syst. II Express Briefs
Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong
2020 J jnl
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation.
IEEE Trans. Very Large Scale Integr. Syst.
Hye-Yoon Joo, Jinhyung Lee, Haram Ju, Han-Gon Ko, Jungmin Yoon, Byungjun Kang, Deog-Kyoon Jeong
2020 J jnl
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2020 — conf
An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference.
ISOCC
Hyojun Kim, Jun-Eun Park, Deog-Kyoon Jeong
2020 — conf
Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS.
ISOCC
Daehyun Koh, Dainel Jeong, Jeongho Hwang, Deog-Kyoon Jeong
2019 — conf
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.
OFC
Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong
2019 — conf
A $4.7\mu \mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS.
ICEIC
Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong
2019 — conf
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level.
VLSI Circuits
Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong
2019 J jnl
A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors.
IEEE Access
Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong
2019 J jnl
A 10-Gb/s, 0.03-mm
IEEE J. Solid State Circuits
Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2019 J jnl
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs
Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong
2019 J jnl
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs
Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim
2019 — conf
A 370-fJ/b, 0.0056 mm
VLSI Circuits
Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong
2019 — conf
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
VLSI Circuits
Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2019 — conf
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
VLSI Circuits
Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong
2019 A conf
A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode.
ISLPED
Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong
2019 — conf
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS.
ICEIC
Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong
2019 — conf
A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation.
A-SSCC
Hye-Yoon Joo, Deog-Kyoon Jeong
2019 J jnl
A Modulo-FIR Equalizer for Wireline Communications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Gyu-Seob Jeong, Byungjun Kang, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2019 J jnl
A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen.
IEEE J. Solid State Circuits
Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong
2019 J jnl
A Noise-Immunity-Enhanced Analog Front-End for $36\times64$ Touch-Screen Controllers With 20- $\text{V}_{\text{PP}}$ Noise Tolerance at 100 kHz.
IEEE J. Solid State Circuits
Jun-Eun Park, Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Deog-Kyoon Jeong
2019 — conf
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm
ISSCC
Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong
2019 — conf
An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC.
ESSCIRC
Young-Ha Hwang, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, Deog-Kyoon Jeong
2019 J jnl
Reference Spur Reduction Techniques for a Phase-Locked Loop.
IEEE Access
Han-Gon Ko, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018 J jnl
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs
Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018 A conf
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.
ISLPED
Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Seong Ho Park, Deog-Kyoon Jeong
2018 — conf
A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS.
A-SSCC
Young-Ha Hwang, Yoonho Song, Jun-Eun Park, Deog-Kyoon Jeong
2018 — conf
A 10-Gb/s, 0.03-mm
A-SSCC
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2018 J jnl
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Jinhyung Lee, Kwanseo Park, Kwangho Lee, Deog-Kyoon Jeong
2018 J jnl
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong
2018 J jnl
A 20 k-to-100kS/s Sub-µW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Ha Hwang, Jun-Eun Park, Yoonho Song, Deog-Kyoon Jeong
2018 J jnl
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018 J jnl
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Hong-Seok Choi, Jeongho Hwang, Gyu-Seob Jeong, Gyungock Kim, Deog-Kyoon Jeong
2018 J jnl
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs
Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim
2018 J jnl
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.
IEEE J. Solid State Circuits
Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong
2018 — conf
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
VLSI Circuits
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog-Kyoon Jeong
2018 — conf
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.
BCICTS
Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2018 — conf
A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit.
VLSI Circuits
Jun-Eun Park, Deog-Kyoon Jeong
2018 J jnl
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron.
Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong
2018 — conf
Adiabatically driven touch controller analog front-end for ultra-thin displays.
CICC
Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong
2018 J jnl
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs
Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2017 — conf
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
ISSCC
Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong
2017 J jnl
A 0.015-mm
IEEE Trans. Circuits Syst. II Express Briefs
Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2017 J jnl
A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong
2017 — conf
A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control.
CICC
Kwanseo Park, Woo-Rham Bae, Deog-Kyoon Jeong
2017 J jnl
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G
IEEE Trans. Circuits Syst. II Express Briefs
Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2017 J jnl
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs
Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
2017 — conf
A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications.
A-SSCC
Young-Ha Hwang, Jun-Eun Park, Deog-Kyoon Jeong
2017 J jnl
Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016).
IEEE J. Solid State Circuits
Deog-Kyoon Jeong, Jaeha Kim
2017 J jnl
Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.
Sensors
Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong
2017 J jnl
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Woo-Rham Bae, Borivoje Nikolic, Deog-Kyoon Jeong
2016 — conf
11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp.
ISSCC
Jun-Eun Park, Jiheon Park, Young-Ha Hwang, Jonghyun Oh, Deog-Kyoon Jeong
2016 J jnl
20-Gb/s 5-V
IEEE Trans. Circuits Syst. II Express Briefs
Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park, Joonbae Park, Gyungock Kim, Deog-Kyoon Jeong
2016 J jnl
A 0.36 pJ/bit, 0.025 mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2016 J jnl
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016 J jnl
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G
IEEE J. Solid State Circuits
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2016 — conf
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.
A-SSCC
Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2016 J jnl
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits
Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2016 C conf
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
ISCAS
Haram Ju, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016 C conf
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS.
ISCAS
Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong
2016 C conf
A theoretical analysis of phase shift in pulse injection-locked oscillators.
ISCAS
Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong
2016 J jnl
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong
2015 C conf
20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS.
ISCAS
Jun-Eun Park, Yoonsoo Kim, Sungwoo Kim, Gyungock Kim, Deog-Kyoon Jeong
2015 — conf
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
A-SSCC
Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim
2015 C conf
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
ISCAS
Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
A-SSCC
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015 J jnl
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2015 — conf
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
ESSCIRC
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
A-SSCC
Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2015 C conf
A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop.
ISCAS
Sungwoo Kim, Sungchun Jang, Jun-Eun Park, Yoonsoo Kim, Gyungock Kim, Deog-Kyoon Jeong
2015 C conf
A low-power pulse position modulation transceiver.
ISCAS
Woo-Rham Bae, Chang-Soo Yoon, Deog-Kyoon Jeong
2015 J jnl
A power-efficient 600-mV
Int. J. Circuit Theory Appl.
Woo-Rham Bae, Deog-Kyoon Jeong
2015 J jnl
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
VLSIC
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2014 J jnl
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS.
IEEE Trans. Very Large Scale Integr. Syst.
Jong-Kwan Woo, Hyunjoong Lee, Hwi-Cheol Kim, Deog-Kyoon Jeong, Suhwan Kim
2014 — conf
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
ESSCIRC
Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2014 C conf
A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS.
ISCAS
Yoonsoo Kim, Woo-Rham Bae, Deog-Kyoon Jeong
2014 C conf
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.
ISCAS
Gyu-Seob Jeong, Hankyu Chi, Kyungock Kim, Deog-Kyoon Jeong
2014 — conf
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
A-SSCC
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2014 J jnl
A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Taeho Kim, Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog-Kyoon Jeong
2014 J jnl
A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels.
IEEE J. Solid State Circuits
Jun-Eun Park, Dong-Hyuk Lim, Deog-Kyoon Jeong
2014 C conf
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.
DDECS
Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo
2014 — conf
A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth.
ICEIC
Woo-Rham Bae, Deog-Kyoon Jeong
2014 J jnl
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator.
IEEE J. Solid State Circuits
Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong
2014 J jnl
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Byoung-Joo Yoo, Woo-Rham Bae, Jiho Han, Jaeha Kim, Deog-Kyoon Jeong
2013 C conf
12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS.
ISCAS
Dong-Wook Kim, Hankyu Chi, Yu-Sang Chun, Myung-Heon Chin, Gyungock Kim, Deog-Kyoon Jeong
2013 — conf
A 0.032mm
ISSCC
Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2013 J jnl
A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM.
IEEE J. Solid State Circuits
Daeyong Shim, Hyunsik Jeong, Hyunjoong Lee, Cyuyeol Rhee, Deog-Kyoon Jeong, Suhwan Kim
2012 — conf
A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology.
ISOCC
Taeho Kim, Deog-Kyoon Jeong
2012 — conf
A low-noise differential front-end and its controller for capacitive touch screen panels.
ESSCIRC
Dong-Hyuk Lim, Jun-Eun Park, Deog-Kyoon Jeong
2012 C conf
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
ISCAS
Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong
2012 — conf
Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface.
ISOCC
Woo-Rham Bae, Byoung-Joo Yoo, Deog-Kyoon Jeong
2011 J jnl
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.
IEEE J. Solid State Circuits
Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong
2011 J jnl
A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control.
IEEE J. Solid State Circuits
Heesoo Song, Deok-Soo Kim, Do-Hwan Oh, Suhwan Kim, Deog-Kyoon Jeong
2011 — conf
A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit.
ISSCC
Sungchun Jang, Heesoo Song, Seokmin Ye, Deog-Kyoon Jeong
2011 — conf
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface.
ISSCC
Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog-Kyoon Jeong, Suhwan Kim
2011 J jnl
A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yohwan Yoon, Deog-Kyoon Jeong
2011 J jnl
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim
2010 J jnl
A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller.
IEEE J. Solid State Circuits
Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, Deog-Kyoon Jeong
2010 J jnl
A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems.
IEEE Trans. Instrum. Meas.
Jiho Han, Deog-Kyoon Jeong
2010 C conf
A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment.
ISCAS
Jiho Han, Hankyu Chi, Deog-Kyoon Jeong
2009 J jnl
A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits
Jeong-Kyoum Kim, Jaeha Kim, Gyudong Kim, Deog-Kyoon Jeong
2009 J jnl
A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification.
IEEE Trans. Circuits Syst. I Regul. Pap.
Young-Deok Kim, Hyun-Seok Ahn, Suhwan Kim, Deog-Kyoon Jeong
2009 — conf
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines.
SoCC
Nan Xing, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim
2009 J jnl
Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Deog-Kyoon Jeong
2009 J jnl
High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer.
IEEE Trans. Consumer Electron.
Jong-Kwan Woo, Dong-Yong Shin, Deog-Kyoon Jeong, Suhwan Kim
2009 J jnl
Practical considerations in the design and implementation of time synchronization systems using IEEE 1588.
IEEE Commun. Mag.
Jiho Han, Deog-Kyoon Jeong
2008 J jnl
An ethernet switch architecture for bandwidth provision of broadband access networks.
IEEE Commun. Mag.
Jonghoon Lee, Chul-Ki Lee, Jiho Han, Hanku Chi, Taesik Na, Deog-Kyoon Jeong, Jae-Hwa Kwak, Jin-su Ahn, Sangho Yoon
2008 J jnl
Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation.
IEEE Trans. Circuits Syst. II Express Briefs
Byoung-Mo Moon, Young-June Park, Deog-Kyoon Jeong
2008 A conf
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.
ICCAD
Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim
2007 J jnl
A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture.
IEEE J. Solid State Circuits
Hoesam Jeong, Byoung-Joo Yoo, Cheol Kyu Han, Sang-Yoon Lee, Kang-Yoon Lee, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim
2007 — conf
A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO.
ISSCC
Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim
2007 J jnl
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme.
IEEE J. Solid State Circuits
Won-Jun Choe, Bong-Joon Lee, Jaeha Kim, Deog-Kyoon Jeong, Gyudong Kim
2007 J jnl
Enhanced token bucket policer using reduced fair queuing for Ethernet access networks.
IET Commun.
Chul-Ki Lee, Jae-Hwa Kwak, Deog-Kyoon Jeong
2007 J jnl
Virtual minimum potential queuing.
J. High Speed Networks
Chul Ki Lee, Deog-Kyoon Jeong, Yong Chul Shim
2006 J jnl
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS.
IEEE J. Solid State Circuits
Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Namhoon Kim, Deog-Kyoon Jeong, Wonchan Kim
2006 — conf
A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm.
ISSCC
Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, Deog-Kyoon Jeong
2006 — conf
A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification.
ISSCC
Young-Deok Kim, Hyun-Seok Ahn, Joon-Young Park, Suhwan Kim, Deog-Kyoon Jeong
2006 J jnl
A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hwi-Cheol Kim, Deog-Kyoon Jeong, Wonchan Kim
2005 J jnl
A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique.
IEEE J. Solid State Circuits
Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Young-Deok Kim, Dohwan Oh, Jaeha Kim, Sang-Hyun Lee, Deog-Kyoon Jeong, Wonchan Kim
2005 J jnl
A single-chip storage LSI for home networks.
IEEE Commun. Mag.
Hankyu Lim, Deog-Kyoon Jeong, Kyungtae Kim, Junmo Park, Han-Gyoo Kim
2005 J jnl
Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer.
IEEE J. Solid State Circuits
Hyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2004 J jnl
A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method.
IEEE J. Solid State Circuits
Jong-Sang Choi, Moon-Sang Hwang, Deog-Kyoon Jeong
2004 J jnl
A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b.
IEEE J. Solid State Circuits
Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Soo-Ik Chae, W. Kim
2004 J jnl
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link.
IEEE J. Solid State Circuits
Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong
2003 J jnl
A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization.
IEEE J. Solid State Circuits
Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, Deog-Kyoon Jeong
2003 — conf
A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b.
ESSCIRC
Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Wonchan Kim
2003 J jnl
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver.
IEEE J. Solid State Circuits
Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2003 J jnl
Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery.
IEEE Trans. Circuits Syst. II Express Briefs
Youngdon Choi, Deog-Kyoon Jeong, Wontae Kim
2003 J jnl
Multi-gigabit-rate clock and data recovery based on blind oversampling.
IEEE Commun. Mag.
Jaeha Kim, Deog-Kyoon Jeong
2002 J jnl
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit.
IEEE J. Solid State Circuits
Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn
2002 J jnl
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems.
IEEE J. Solid State Circuits
Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2001 J jnl
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery.
IEEE J. Solid State Circuits
Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn
2001 J jnl
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique.
IEEE J. Solid State Circuits
Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim
2000 J jnl
A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission.
IEEE J. Solid State Circuits
Gijung Ahn, Deog-Kyoon Jeong, Gyudong Kim
2000 J jnl
A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers.
IEEE J. Solid State Circuits
Jong-Seok Kim, Deog-Kyoon Jeong, Gyudong Kim
2000 J jnl
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.
IEEE J. Solid State Circuits
Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
1999 — conf
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells.
CICC
Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
1998 J jnl
1.04 GBd low EMI digital video interface system using small swing serial link technique.
IEEE J. Solid State Circuits
Kyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog-Kyoon Jeong, Gyudong Kim, Bruce Kim, Victor Da Costa
1998 J jnl
A 32×32-b adiabatic register file with supply clock generator.
IEEE J. Solid State Circuits
Yong Moon, Deog-Kyoon Jeong
1998 B conf
Design and Implementation of OTCA MAC Protocol for High-Speed Point-to-Point Ring Network.
LCN
Yeshik Shin, Jin-su Ahn, Hyung-Rok Lee, Deog-Kyoon Jeong
1997 J jnl
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.
IEEE J. Solid State Circuits
Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim
1996 J jnl
An efficient charge recovery logic circuit.
IEEE J. Solid State Circuits
Yong Moon, Deog-Kyoon Jeong
1995 J jnl
A CMOS serial link for fully duplexed data communication.
IEEE J. Solid State Circuits
Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong
1995 J jnl
A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem.
IEEE J. Solid State Circuits
Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim
1995 A* conf
U-Cache: A Cost-Effective Solution to the Synonym Problem.
HPCA
Jesung Kim, Sang Lyul Min, Sanghoon Jeon, Byoungchul Ahn, Deog-Kyoon Jeong, Chong-Sang Kim
1994 C conf
A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter.
ISCAS
Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim
1994 — conf
Hotpads - macro-dells for gigabit I/O.
Hot Interconnects
Deog-Kyoon Jeong, David D. Lee, J. Duane Northcutt, Andreas von Bechtolsheim, David R. Ditzel, Amnon Fisher
1993 J jnl
Class-AB large-swing CMOS buffer amplifier with controlled bias current.
IEEE J. Solid State Circuits
Joongsik Kih, Byungsoo Chang, Deog-Kyoon Jeong
1993 J jnl
Threaded prefetching: An adaptive instruction prefetch mechanism.
Microprocess. Microprogramming
Seong Baeg Kim, Myung Soon Park, Sun-Ho Park, Sang Lyul Min, Heonshik Shin, Chong-Sang Kim, Deog-Kyoon Jeong
1993 J jnl
V-P cache: a storage efficient virtual cache organization.
Microprocess. Microsystems
Sang Lyul Min, Jesung Kim, Chong-Sang Kim, Heonshik Shin, Deog-Kyoon Jeong
1992 J jnl
An experimental single-chip data flow CPU.
IEEE J. Solid State Circuits
Gregory A. Uvieghara, Wen-mei W. Hwu, Yoshinobu Nakagome, Deog-Kyoon Jeong, David D. Lee, David A. Hodges, Yale N. Patt
1990 J jnl
An on-chip smart memory for a data-flow CPU.
IEEE J. Solid State Circuits
Gregory A. Uvieghara, Yoshinobu Nakagome, Deog-Kyoon Jeong, David A. Hodges
1989 J jnl
A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller.
IEEE J. Solid State Circuits
Deog-Kyoon Jeong, David A. Wood, Garth A. Gibson, Susan J. Eggers, David A. Hodges, Randy H. Katz, David A. Patterson