Dennis Walter - RankMe

37 papers A* 2A 2B 3C 1Journal 13Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications. IEEE Open J. Circuits Syst. Amirhossein Rostami, Seyed Mohammad Ali Zeinolabedin, Liyuan Guo, Florian Kelber, Heiner Bauer, Andreas Dixius, Stefan Scholze, Marc Berthel, Dennis Walter, Johannes Uhlig, Bernhard Vogginger, Christian Mayr
2023	—	`conf`	A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. CICC Hector A. Gonzalez, Bernhard Vogginger, Chen Liu, Marco Stolba, Florian Kelber, Heiner Bauer, Stefan Hänzsche, Stefan Scholze, Marc Berthel, Tim Rosmeisl, Liyuan Guo, Dennis Walter, Piash Das, Khaleelulla Khan Nazeer, Tilo Schubert, Sebastian Höppner, Christian Mayr
2023	—	`conf`	A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. ISOCC Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich
2023	J	`jnl`	A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. CoRR Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich
2022	J	`jnl`	A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. IEEE Trans. Biomed. Circuits Syst. Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Richard George, Florian Kelber, Heiner Bauer, Stefan Scholze, Stefan Hänzsche, Marco Stolba, Andreas Dixius, Georg Ellguth, Dennis Walter, Sebastian Höppner, Christian Mayr
2022	—	`conf`	ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data. AICAS Matthias Jobst, Johannes Partzsch, Chen Liu, Liyuan Guo, Dennis Walter, Saif-Ur Rehman, Stefan Scholze, Sebastian Höppner, Christian Mayr
2021	J	`jnl`	Hardware Implementation of an OPC UA Server for Industrial Field Devices. CoRR Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr
2021	J	`jnl`	Hardware Implementation of an OPC UA Server for Industrial Field Devices. IEEE Trans. Very Large Scale Integr. Syst. Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr
2021	J	`jnl`	The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. CoRR Sebastian Höppner, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Marco Stolba, Florian Kelber, Bernhard Vogginger, Felix Neumärker, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Thomas Hocker, Dennis Walter, Gengting Liu, Jim D. Garside, Steve B. Furber, Christian Mayr
2020	—	`conf`	A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. COOL CHIPS Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner
2020	J	`jnl`	Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. IEEE Trans. Circuits Syst. II Express Briefs Sebastian Höppner, Holger Eisenreich, Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Jörg Schreiter, Thorsten Riedel, Heiner Bauer, Robert Niebsch, Stephan Scherzer, Thomas Hocker, Stefan Scholze, Stephan Henker, Matthias Nossmann, Ulrich Hensel, Helmut Prengel
2019	—	`conf`	How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. ESSDERC Sebastian Höppner, Jörg Schreiter, Robert Niebsch, Stephan Scherzer, Ulrich Hensel, Jörg Winkler, Mario Orgis, Holger Eisenreich, Dennis Walter, Uwe Steeb, André Scharfe, Clifford Dmello, Robert Sinkwitz, Heiner Bauer, Alexander Oefelein, Florian Schraut
2018	A	`conf`	A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. DATE Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar
2017	A*	`conf`	A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. DAC Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis
2017	A	`conf`	Exploiting transistor-level reconfiguration to optimize combinational circuits. DATE Michael Raitza, Akash Kumar, Marcus Völp, Dennis Walter, Jens Trommer, Thomas Mikolajick, Walter M. Weber
2017	—	`conf`	Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. NORCAS Heiner Bauer, Sebastian Höppner, Johannes Partzsch, Dennis Walter, Christian Mayr, Florian Schraut, Holger Eisenreich
2016	A*	`conf`	An MPSoC for energy-efficient database query processing. DAC Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis
2015	—	`conf`	A deep-submicron CMOS flow for general-purpose timing-detection insertion. MIXDES Andreas Dixius, Dennis Walter, Sebastian Höppner, Holger Eisenreich, René Schüffny
2015	J	`jnl`	An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. IEEE J. Solid State Circuits Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny
2014	—	`conf`	10.7 A 105GOPS 36mm ISSCC Benedikt Noethen, Oliver Arnold, Esther P. Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, J.-U. Schlusler, Stefan Scholze, Dennis Walter, René Schüffny
2014	—	`conf`	An energy efficient multi-bit TSV transmitter using capacitive coupling. ICECS Johannes Gorner, Sebastian Höppner, Dennis Walter, Michael Haas, Dirk Plettemeier, René Schüffny
2013	J	`jnl`	A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny
2013	J	`jnl`	A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Sebastian Höppner, Stefan Hänzsche, Georg Ellguth, Dennis Walter, Holger Eisenreich, René Schüffny
2013	—	`conf`	Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology. ECCTD Sebastian Höppner, Dennis Walter, Holger Eisenreich, Stefan Schiefer, René Schüffny
2012	—	`conf`	A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. ISSCC Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard P. Fettweis
2012	J	`jnl`	Guaranteeing functional safety: design for provability and computer-aided verification. Auton. Robots Holger Täubig, Udo Frese, Christoph Hertzberg, Christoph Lüth, Stefan Mohr, Elena Vorobev, Dennis Walter
2012	J	`jnl`	On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. Int. J. Embed. Real Time Commun. Syst. Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny
2011	—	`conf`	Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. SoC Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny
2010	—	`—`	A formal verification environment for use in the certification of safety-related C-programs. Dennis Walter
2010	—	`conf`	Efficient compensation of delay variations in high-speed network-on-chip data links. SoC Sebastian Höppner, Dennis Walter, Holger Eisenreich, René Schüffny
2010	B	`conf`	Experiences in Applying Formal Verification in Robotics. SAFECOMP Dennis Walter, Holger Täubig, Christoph Lüth
2009	B	`conf`	Certifiable Specification and Verification of C Programs. FM Christoph Lüth, Dennis Walter
2008	J	`jnl`	Integration of a security type system into a program logic. Theor. Comput. Sci. Reiner Hähnle, Jing Pan, Philipp Rümmer, Dennis Walter
2008	—	`conf`	The Importance of Being Formal. SafeCert@ETAPS Udo Frese, Daniel Hausmann, Christoph Lüth, Holger Täubig, Dennis Walter
2008	C	`conf`	Zertifizierung einer Sicherungskomponente mittels durchgängig formaler Modellierung. Software Engineering (Workshops) Udo Frese, Daniel Hausmann, Christoph Lüth, Holger Täubig, Dennis Walter
2006	—	`conf`	Integration of a Security Type System into a Program Logic. TGC Reiner Hähnle, Jing Pan, Philipp Rümmer, Dennis Walter
2005	B	`conf`	Parametrized Exceptions. CALCO Dennis Walter, Lutz Schröder, Till Mossakowski