Denis Deschacht

17 papers Misc 1Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2010 J jnl
Crosstalk pulsewidth calculation.
Microelectron. J.
Jean-Etienne Lorival, Denis Deschacht
2006 J jnl
DSM interconnects: importance of inductance effects and corresponding range of length.
IEEE Trans. Very Large Scale Integr. Syst.
Denis Deschacht
2005 Misc conf
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation.
VLSI Design
Denis Deschacht, Alain Lopez
2004 — conf
Comparison between Different Data Buses Configurations.
ISVLSI
Alain Lopez, Denis Deschacht
2002 — conf
Impact of Low-K on Crosstalk.
ISQED
Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret
2001 — conf
On-chip interconnections: impact of adjacent lines on timing.
ASP-DAC
Denis Deschacht, Grégory Servel
2000 — conf
On-chip crosstalk evaluation between adjacent interconnections.
ICECS
Grégory Servel, Denis Deschacht
2000 — conf
Theoretical limits for signal reflections due to inductance for on-chip interconnections.
SLIP
Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis
1999 — conf
Inductance effect for interconnection timing analysis in submicronic circuits.
ICECS
Grégory Servel, L. B. Kenmei, Fabrice Huret, Erick Paleczny, Patrick Kennis, Denis Deschacht
1996 J jnl
Delay propagation effect in transistor gates.
IEEE J. Solid State Circuits
Denis Deschacht, Christophe Dabrin, Daniel Auvergne
1995 — conf
A new and accurate interconnection delay time evaluation in a general tree-type network.
ASP-DAC
Denis Deschacht, Christophe Dabrin
1993 J jnl
Post-layout timing simulation of CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne
1991 — conf
Formal sizing rules of CMOS circuits.
EURO-DAC
Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert
1991 J jnl
Synchronous-mode evaluation of delays in CMOS structures.
IEEE J. Solid State Circuits
Denis Deschacht, Michel Robert, Daniel Auvergne
1991 J jnl
TVA: A timing verifier with analytic temporal modelling.
Microprocessing and Microprogramming
D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne
1990 J jnl
Input waveform slope effects in CMOS delays.
IEEE J. Solid State Circuits
Daniel Auvergne, Nadine Azémard, Denis Deschacht, Michel Robert
1990 — conf
Path runner: an accurate and fast timing analyser.
EURO-DAC
Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne