Dengquan Li

40 papers C 1Journal 32Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Reconfigurable Voltage-Time Hybrid ADC With Quantization Threshold Shifting and Common-Mode Tracking.
IEEE Trans. Circuits Syst. II Express Briefs
Depan Li, Dengquan Li, Yubo Yan, Yexin Zhu, Zhangming Zhu
2025 — conf
24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier.
ISSCC
Yue Cao, Yi Shen, Shubin Liu, Haolin Han, Hongzhi Liang, Li Dang, Dengquan Li, Ruixue Ding, Zhangming Zhu
2025 J jnl
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.
IEEE J. Solid State Circuits
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
2025 — conf
A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier.
CICC
Xin Zhao, Dengquan Li, Feida Wang, Depan Li, Yi Shen, Hongzhi Liang, Zhangming Zhu
2025 J jnl
A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler.
IEEE Solid State Circuits Lett.
Dengquan Li, Maowen Qian, Depan Li, Hongzhi Liang, Zhangming Zhu
2025 J jnl
FR-CNN: Frequency Recognition Convolutional Neural Network-Based Calibration for Timing Skew in TI-ADCs.
IEEE Trans. Circuits Syst. II Express Briefs
Dengquan Li, Tianqi Yang, Longsheng Wang, Shuai Lang, Hongzhi Liang, Zhangming Zhu
2024 J jnl
A 0.55-mm
Microelectron. J.
Jiale Ding, Yukai Huang, Hao Zhang, Tian Feng, Feida Wang, Dengquan Li, Zhangming Zhu
2024 J jnl
A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs
Hongzhi Liang, Shubin Liu, Ruixue Ding, Yi Shen, Dengquan Li, Zhangming Zhu
2024 J jnl
A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.
IEEE Trans. Instrum. Meas.
Dengquan Li, Longsheng Wang, Yi Shen, Shubin Liu, Zhangming Zhu
2024 J jnl
A Wideband Input Buffer Based on Cascade Complementary Source Follower.
IEEE Trans. Very Large Scale Integr. Syst.
Dengquan Li, Tian Feng, Jiale Ding, Yi Shen, Shubin Liu, Zhangming Zhu
2024 J jnl
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Longsheng Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu
2024 J jnl
LUT-Assisted Particle Swarm Optimization-Based Bit-Weight Calibration for SAR ADCs.
IEEE Trans. Instrum. Meas.
Longsheng Wang, Dengquan Li, Yexin Zhu, Shubin Liu, Ruixue Ding, Zhangming Zhu
2024 C conf
Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting.
ISCAS
Dengquan Li, Yexin Zhu, Longsheng Wang, Shubin Liu, Zhangming Zhu
2023 — conf
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
CICC
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
2023 J jnl
A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dengquan Li, Xin Zhao, Yi Shen, Shubin Liu, Zhangming Zhu
2023 J jnl
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.
IEEE Trans. Very Large Scale Integr. Syst.
Yi Shen, Junyan Hao, Shubin Liu, Zeshuai An, Dengquan Li, Ruixue Ding, Zhangming Zhu
2023 J jnl
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.
IEEE Trans. Very Large Scale Integr. Syst.
Xin Zhao, Dengquan Li, Feida Wang, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2022 J jnl
A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Maliang Liu, Chenxi Zhang, Shubin Liu, Dengquan Li
2022 J jnl
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
Dengquan Li, Lei Zhao, Longsheng Wang, Yi Shen, Zhangming Zhu
2022 J jnl
A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs.
IEEE Trans. Circuits Syst. II Express Briefs
Depeng Sun, Ruixue Ding, Feng Bu, Hongzhi Liang, Dengquan Li, Yuhua Liang, Shubin Liu
2022 — conf
A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower.
ICTA
Tian Feng, Dengquan Li, Jiale Ding, Shubin Liu, Yi Shen, Zhangming Zhu
2022 J jnl
A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS.
Microelectron. J.
Henghui Mao, Dengquan Li, Shubin Liu
2022 J jnl
A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration.
Microelectron. J.
Yukai Huang, Jiale Ding, Dengquan Li, Xin Zhao, Shubin Liu, Yi Shen, Zhangming Zhu
2022 J jnl
Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs.
Circuits Syst. Signal Process.
Jiale Ding, Yukai Huang, Dengquan Li, Shubin Liu, Yi Shen, Zhangming Zhu
2022 J jnl
Radio frequency analog-to-digital converters: Systems and circuits review.
Microelectron. J.
Dengquan Li, Xin Zhao, Shubin Liu, Maliang Liu, Ruixue Ding, Yuhua Liang, Zhangming Zhu
2021 — conf
27.1 A 250kHz-BW 93dB-SNDR 4
ISSCC
Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun
2021 J jnl
A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS.
J. Circuits Syst. Comput.
Lei Zhao, Dengquan Li, Henghui Mao, Ruixue Ding, Zhangming Zhu
2021 J jnl
A TD-ADC for IR-UWB Radars With Equivalent Sampling Technology and 8-GS/s Effective Sampling Rate.
IEEE Trans. Circuits Syst. II Express Briefs
Zhangming Zhu, Yu Zhu, Dengquan Li, Maliang Liu
2021 J jnl
A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs.
Microelectron. J.
Dengquan Li, Maliang Liu, Shubin Liu, Yuhua Liang, Ruixue Ding
2020 J jnl
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration.
IEEE J. Solid State Circuits
Dengquan Li, Zhangming Zhu, Jiaxin Liu, Haoyu Zhuang, Yintang Yang, Nan Sun
2020 J jnl
A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application.
IEEE Trans. Circuits Syst. II Express Briefs
Maliang Liu, Dengquan Li, Zhangming Zhu
2020 J jnl
An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS.
IEEE Trans. Circuits Syst.
Dengquan Li, Maliang Liu, Lei Zhao, Henghui Mao, Ruixue Ding, Zhangming Zhu
2019 J jnl
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Dengquan Li, Zhangming Zhu, Ruixue Ding, Maliang Liu, Yintang Yang, Nan Sun
2019 — conf
A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration.
CICC
Dengquan Li, Jiaxin Liu, Haoyu Zhuang, Zhangming Zhu, Yintang Yang, Nan Sun
2018 J jnl
A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Dengquan Li, Zhangming Zhu, Ruixue Ding, Yintang Yang
2018 J jnl
A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS.
Microelectron. J.
Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu
2018 — conf
A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation.
APCCAS
Dengquan Li, Ruixue Ding, Zhangming Zhu, Yintang Yang
2016 J jnl
A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS.
J. Circuits Syst. Comput.
Liang Zhang, Dengquan Li, Zhangming Zhu, Yintang Yang
2016 J jnl
A background fast convergence algorithm for timing skew in time-interleaved ADCs.
Microelectron. J.
Dengquan Li, Zhangming Zhu, Liang Zhang, Yintang Yang
2015 J jnl
An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS.
J. Circuits Syst. Comput.
Dengquan Li, Liang Zhang, Zhangming Zhu, Yintang Yang