Deepak Mathaikutty

51 papers A 1B 1C 8Misc 3Journal 17Unranked 19

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Softprox: A Post-Finetuning Methodology to Mitigate Softmax Bottlenecks in Transformer Workloads. IEEE Trans. Circuits Syst. Artif. Intell. Aradhana Mohan Parvathy, Sourjya Roy, Soumendu Kumar Ghosh, Arnab Raha, Deepak Mathaikutty, Anand Raghunathan
2025	J	`jnl`	Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset. CoRR Anand Menon, Samit S. Miftah, Shamik Kundu, Souvik Kundu, Amisha Srivastava, Arnab Raha, Gabriel Theodor Sonnenschein, Suvadeep Banerjee, Deepak Mathaikutty, Kanad Basu
2025	B	`conf`	GraNNite: Enabling High-Performance Execution of Graph Neural Networks on Resource-Constrained Neural Processing Units. IJCNN Arghadip Das, Shamik Kundu, Arnab Raha, Soumendu Kumar Ghosh, Deepak Mathaikutty, Vijay Raghunathan
2025	J	`jnl`	GraNNite: Enabling High-Performance Execution of Graph Neural Networks on Resource-Constrained Neural Processing Units. CoRR Arghadip Das, Shamik Kundu, Arnab Raha, Soumendu Kumar Ghosh, Deepak Mathaikutty, Vijay Raghunathan
2025	Misc	`conf`	OpenAssert: Towards Secure Assertion Generation using Large Language Models. VTS Anand Menon, Samit Shahnawaz Miftah, Amisha Srivastava, Shamik Kundu, Shovik Kundu, Arnab Raha, Suvadeep Banerjee, Deepak Mathaikutty, Kanad Basu
2025	J	`jnl`	XAMBA: Enabling Efficient State Space Models on Resource-Constrained Neural Processing Units. CoRR Arghadip Das, Arnab Raha, Shamik Kundu, Soumendu Kumar Ghosh, Deepak Mathaikutty, Vijay Raghunathan
2023	J	`jnl`	VPU-EM: An Event-based Modeling Framework to Evaluate NPU Performance and Power Efficiency at Scale. CoRR Charles Qi, Yi Wang, Hui Wang, Yang Lu, Shiva Shankar Subramanian, Finola Cahill, Conall Tuohy, Victor Li, Xu Qian, Darren Crews, Ling Wang, Shivaji Roy, Andrea Deidda, Martin Power, Niall Hanrahan, Rick Richmond, Umer Cheema, Arnab Raha, Alessandro Palla, Gary Baugh, Deepak Mathaikutty
2023	—	`conf`	Wireless-Assisted Automatic Online Spatial Calibration based on 5G TSN for Sensor Fusion. ICSPCC Ming Lei, Mahib Rahman, Deepak Mathaikutty, Ignacio Alvarez
2022	—	`conf`	2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. VLSI Technology and Circuits Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De
2021	Misc	`conf`	Design Considerations for Edge Neural Network Accelerators: An Industry Perspective. VLSID Arnab Raha, Sang Kyun Kim, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Raymond Sung, Cormac Brick, Gautham N. Chinya
2019	J	`jnl`	An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018	—	`conf`	An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018	J	`jnl`	Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham N. Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios D. Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steven McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, Hong Wang
2009	—	`conf`	Accurate power estimation of hardware co-processors using system level simulation. SoCC Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla
2009	—	`book`	Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design. Deepak Mathaikutty, Sandeep Kumar Shukla
2009	J	`jnl`	Metamodeling: An Emerging Representation Paradigm for System-Level Design. IEEE Des. Test Comput. Alberto L. Sangiovanni-Vincentelli, Sandeep K. Shukla, Janos Sztipanovits, Guang Yang, Deepak Mathaikutty
2009	—	`conf`	Power estimation methodology for a high-level synthesis framework. ISQED Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar
2008	J	`jnl`	A Trace-Based Framework for Verifiable GALS Composition of IPs. IEEE Trans. Very Large Scale Integr. Syst. Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2008	—	`conf`	Applying Verification Collaterals for Accurate Power Estimation. MTV Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla
2008	C	`conf`	Formal Transformation of a KPN Specification to a GALS Implementation. FDL Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty
2008	J	`jnl`	MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models. IEEE Trans. Very Large Scale Integr. Syst. Deepak Mathaikutty, Sandeep K. Shukla
2008	J	`jnl`	MMV: A Metamodeling Based Microprocessor Validation Environment. IEEE Trans. Very Large Scale Integr. Syst. Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja
2008	J	`jnl`	Mining metadata for composability of IPs from SystemC IP library. Des. Autom. Embed. Syst. Deepak Mathaikutty, Sandeep K. Shukla
2008	J	`jnl`	SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system. Des. Autom. Embed. Syst. Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch
2007	C	`conf`	A Metamodeling based Framework for Architectural Modeling and Simulator Generation. FDL Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla
2007	—	`conf`	Assertion-Based Modal Power Estimation. MTV Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar
2007	—	`conf`	Dataflow Architectures for GALS. FMGALS@MEMOCODE Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2007	A	`conf`	Design fault directed test generation for microprocessor validation. DATE Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar
2007	J	`jnl`	EWD: A metamodeling driven customizable multi-MoC system modeling framework. ACM Trans. Design Autom. Electr. Syst. Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch
2007	—	`—`	Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design. Deepak Mathaikutty
2007	Misc	`conf`	Model Based Test Generation for Microprocessor Architecture Validation. VLSI Design Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja
2007	—	`conf`	Model-driven test generation for system level validation. HLDVT Deepak Mathaikutty, Sumit Ahuja, Ajit Dingankar, Sandeep K. Shukla
2007	C	`conf`	Type Inference for IP Composition. MEMOCODE Deepak Mathaikutty, Sandeep K. Shukla
2006	—	`conf`	A Trace Based Framework for Validation of SoC Designs with GALS Systems. SoCC Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2006	J	`jnl`	CARH: service-oriented architecture for validating system-level designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiren D. Patel, Deepak Mathaikutty, David Berner, Sandeep K. Shukla
2006	C	`conf`	MCF: A Metamodeling-based Visual Component Composition Framework. FDL Deepak Mathaikutty, Sandeep K. Shukla
2006	—	`conf`	MMV: Metamodeling Based Microprocessor Valiation Environment. HLDVT Ajit Dingankar, Deepak Mathaikutty, Sreekumar V. Kodakara, Sandeep K. Shukla, David J. Lilja
2006	C	`conf`	Mining Metadata for Composability of IPs from SystemC IP Library. FDL Deepak Mathaikutty, Sandeep K. Shukla
2006	—	`conf`	Polychronous Methodology For System Design: A True Concurrency Approach. HLDVT Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, Jean-Pierre Talpin
2006	—	`conf`	SoC Design Space Exploration through Automated IP Selection from SystemC IP Library. SoCC Deepak Mathaikutty, Sandeep K. Shukla
2006	J	`jnl`	Validating Families of Latency Insensitive Protocols. IEEE Trans. Computers Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla
2005	—	`conf`	A Functional Programming Framework for Latency Insensitive Protocol Validation. FMGALS@MEMOCODE Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin
2005	—	`conf`	Automated Extraction of Structural Information from SystemC-based IP for Validation. MTV David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla
2005	C	`conf`	Modelling Environment for Heterogeneous Systems based on MoCs. FDL Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch
2005	—	`conf`	System Level Design Methodology for System On Chips using Multi-Threaded Graphs. SoCC Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2005	C	`conf`	SystemCXML: An Exstensible SystemC Front end Using XML. FDL David Berner, Jean-Pierre Talpin, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla
2005	—	`conf`	Validating families of latency insensitive protocols. HLDVT Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
2005	J	`jnl`	XFM: An incremental methodology for developing formal models. ACM Trans. Design Autom. Electr. Syst. Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
2004	C	`conf`	A Functional Programming Framework of Heterogeneous Model of Computation for System Design. FDL Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla
2004	—	`conf`	Effects of property ordering in an incremental formal modeling methodology. HLDVT Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2004	—	`conf`	Extreme Formal Modeling (XFM) for Hardware Models. MTV Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner