Deepak Kachave

11 papers Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2019 J jnl
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anirban Sengupta, Deepak Kachave, Dipanjan Roy
2018 J jnl
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Comput. Digit. Tech.
Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha
2018 J jnl
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis.
Future Gener. Comput. Syst.
Anirban Sengupta, Deepak Kachave
2018 — conf
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores.
iSES
Anirban Sengupta, Deepak Kachave
2018 J jnl
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters].
IEEE Consumer Electron. Mag.
Deepak Kachave, Anirban Sengupta
2018 J jnl
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath.
IEEE Trans. Aerosp. Electron. Syst.
Anirban Sengupta, Deepak Kachave
2017 J jnl
Low cost fault tolerance against k
Microelectron. Reliab.
Anirban Sengupta, Deepak Kachave
2017 — conf
Reliability and Threat Analysis of NBTI Stress on DSP Cores.
iNIS
Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha
2016 — conf
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
ISVLSI
Anirban Sengupta, Deepak Kachave
2016 J jnl
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.
Microelectron. Reliab.
Deepak Kachave, Anirban Sengupta
2016 — conf
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis.
iNIS
Deepak Kachave, Anirban Sengupta