Debjit Sinha

33 papers A* 9A 10Misc 2Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2021 A conf
Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure.
DATE
Ravi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile
2020 A* conf
Statistical Timing Analysis considering Multiple-Input Switching.
DAC
Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams
2016 A* conf
A distributed timing analysis framework for large designs.
DAC
Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran
2016 A conf
Generation and use of statistical timing macro-models considering slew and load variability.
ICCAD
Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey
2016 A* conf
Practical statistical static timing analysis with current source models.
DAC
Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala
2016 Misc conf
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.
VLSID
Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma
2016 A* conf
Statistical path tracing in timing graphs.
DAC
Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya
2014 A conf
TAU 2014 contest on removing common path pessimism during timing analysis.
ICCAD
Jin Hu, Debjit Sinha, Igor Keller
2014 — conf
TAU 2014 contest on removing common path pessimism during timing analysis.
ISPD
Jin Hu, Debjit Sinha, Igor Keller
2013 A* conf
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization.
DAC
Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan
2013 — conf
TAU 2013 variation aware timing analysis contest.
ISPD
Debjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita
2012 A* conf
Reversible statistical
DAC
Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov
2012 A* conf
Timing analysis with nonseparable statistical and deterministic variations.
DAC
Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran
2009 J jnl
A Timing-Dependent Power Estimation Framework Considering Coupling.
IEEE Trans. Very Large Scale Integr. Syst.
DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail
2009 J jnl
Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debjit Sinha, Alex Rubin, Chandu Visweswariah, Frank Borkam, Gregory Schaeffer, Soroush Abbaspour
2008 A conf
Constrained aggressor set selection for maximum coupling noise.
ICCAD
Debjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam
2008 A* conf
Driver waveform computation for timing analysis with multiple voltage threshold driver models.
DAC
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta
2007 J jnl
Advances in Computation of the Maximum of a Set of Gaussian Random Variables.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debjit Sinha, Hai Zhou, Narendra V. Shenoy
2007 Misc conf
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
VLSI Design
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
2007 J jnl
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
2006 A conf
A timing dependent power estimation framework considering coupling.
ICCAD
Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
2006 — conf
Advances in Computation of the Maximum of a Set of Random Variables.
ISQED
Debjit Sinha, Hai Zhou, Narendra V. Shenoy
2006 J jnl
Gate-size optimization under timing constraints for coupling-noise reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debjit Sinha, Hai Zhou
2006 A conf
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.
DATE
Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
2006 J jnl
Statistical Timing Analysis With Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debjit Sinha, Hai Zhou
2006 J jnl
Statistical Timing Yield Optimization by Gate Sizing.
IEEE Trans. Very Large Scale Integr. Syst.
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2006 A* conf
Yield-Aware Cache Architectures.
MICRO
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
2005 A conf
A unified framework for statistical timing analysis with coupling and multiple input switching.
ICCAD
Debjit Sinha, Hai Zhou
2005 A conf
Statistical gate sizing for timing yield optimization.
ICCAD
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
2005 — conf
Yield driven gate sizing for coupling-noise reduction under uncertainty.
ASP-DAC
Debjit Sinha, Hai Zhou
2004 A conf
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.
FPGA
Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee
2004 A conf
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.
ICCAD
Debjit Sinha, Hai Zhou
2004 — conf
Optimal gate sizing for coupling-noise reduction.
ISPD
Debjit Sinha, Hai Zhou, Chris C. N. Chu