Debiprasanna Sahoo

14 papers A 2C 2Misc 4Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2025 — conf
PEEP: A Tool for PErformance Effect Prediction.
HiPCW
G. Ramya Sri, Debiprasanna Sahoo, Ajaya Kumar Dash
2023 J jnl
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
2020 A conf
Fuzzy fairness controller for NVMe SSDs.
ICS
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
2020 A conf
Slumber: static-power management for GPGPU register files.
ISLPED
Devashree Tripathy, Hadi Zamani, Debiprasanna Sahoo, Laxmi N. Bhuyan, Manoranjan Satpathy
2019 C conf
Formal Modeling and Verification of NAND Flash Memory Supporting Advanced Operations.
ICCD
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Srinivas Pinisetty
2019 J jnl
Formal Modeling and Verification of a Victim DRAM Cache.
ACM Trans. Design Autom. Electr. Syst.
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
2019 Misc conf
Multidimensional Grid Aware Address Prediction for GPGPU.
VLSID
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy
2019 C conf
Post-Model Validation of Victim DRAM Caches.
ICCD
Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam
2018 — conf
CAMO: A novel cache management organization for GPGPUs.
ASP-DAC
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan
2018 Misc conf
DRAM cache access optimization leveraging line locking in tag cache: work-in-progress.
CASES
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy
2018 J jnl
Formal Modeling and Verification of Controllers for a Family of DRAM Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
2018 J jnl
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs.
IEEE Comput. Archit. Lett.
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam
2017 Misc conf
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors.
VLSID
Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
2016 Misc conf
MSimDRAM: Formal Model Driven Development of a DRAM Simulator.
VLSID
Debiprasanna Sahoo, Manoranjan Satpathy