Debesh Kumar Das

47 papers A 1C 2Misc 7Journal 17Unranked 20

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A Novel TSV Repair Framework for 3-D Stacked ICs. ATS Tanusree Kaibartta, Rajiv Murmu, Debesh Kumar Das
2024	C	`conf`	Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. DSD Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das
2024	J	`jnl`	Design-for-testability for reversible logic circuits based on bit-swapping. IET Quantum Commun. Joyati Mondal, Debesh Kumar Das, Bhargab B. Bhattacharya
2024	Misc	`conf`	Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. VLSID Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das
2024	J	`jnl`	IRUVD: a new still-image based dataset for automatic vehicle detection. Multim. Tools Appl. Asfak Ali, Ram Sarkar, Debesh Kumar Das
2024	—	`conf`	Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars. VDAT Pragnya Dhal, Arighna Deb, Subrata Das, Debesh Kumar Das
2022	J	`jnl`	A new online testing technique for reversible circuits. IET Quantum Commun. Joyati Mondal, Debesh Kumar Das
2022	J	`jnl`	DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. J. Circuits Syst. Comput. Joyati Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das, Bhargab B. Bhattacharya
2022	—	`conf`	Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. VDAT Subrata Das, Debesh Kumar Das, Soumya Pandit
2021	J	`jnl`	A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC. IEEE Access Tanusree Kaibartta, G. P. Biswas, Arup Kumar Pal, Debesh Kumar Das
2021	Misc	`conf`	Minimization of Switching Activity of Graphene Based Circuits. VLSID Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das
2020	J	`jnl`	A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. ACM J. Emerg. Technol. Comput. Syst. Subrata Das, Debesh Kumar Das, Soumya Pandit
2020	J	`jnl`	A Novel ALU Circuit based on Reversible Logic. J. Circuits Syst. Comput. Arindam Banerjee, Debesh Kumar Das
2020	—	`conf`	An Improved Online Testing Technique For Reversible Circuits. ISDCS Joyati Mondal, Debesh Kumar Das
2020	J	`jnl`	Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs. J. Electron. Test. Tanusree Kaibartta, G. P. Biswas, Debesh Kumar Das
2019	J	`jnl`	Approach of genetic algorithm for power-aware testing of 3D IC. IET Comput. Digit. Tech. Tanusree Kaibartta, Chandan Giri, Hafizur Rahaman, Debesh Kumar Das
2019	—	`conf`	Arithmetic Circuits Using Reversible Logic: A Survey Report. ACSS (1) Arindam Banerjee, Debesh Kumar Das
2019	J	`jnl`	Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. J. Circuits Syst. Comput. Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das
2018	—	`conf`	Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. ISVLSI Subrata Das, Debesh Kumar Das
2018	—	`conf`	Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach. VDAT Tanusree Kaibartta, Debesh Kumar Das
2017	—	`conf`	A technique to construct global routing trees for graphene nanoribbon (GNR). ISQED Subrata Das, Debesh Kumar Das
2017	—	`conf`	Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing. ATS Joyati Mondal, Debesh Kumar Das
2016	J	`jnl`	A New Squarer design with reduced area and delay. IET Comput. Digit. Tech. Arindam Banerjee, Debesh Kumar Das
2016	—	`conf`	A new ALU architecture design using reversible logic. ISED Arindam Banerjee, Debesh Kumar Das
2016	C	`conf`	A rule-based approach for minimizing power dissipation of digital circuits. DDECS Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das
2016	—	`conf`	Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees. ACM Great Lakes Symposium on VLSI Subrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das
2016	—	`conf`	Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. VDAT Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das
2016	Misc	`conf`	Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. VLSID Arindam Banerjee, Debesh Kumar Das
2015	J	`jnl`	One More Class of Sequential Circuits having Combinational Test Generation Complexity. J. Electron. Test. Debesh Kumar Das, Hideo Fujiwara
2015	—	`conf`	Squarer design with reduced area and delay. VDAT Arindam Banerjee, Debesh Kumar Das
2015	J	`jnl`	The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. J. Low Power Electron. Arindam Banerjee, Debesh Kumar Das
2014	J	`jnl`	A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. J. Low Power Electron. Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay
2014	—	`conf`	A regular network of symmetric functions in quantum-dot cellular automata. VDAT Arighna Deb, Debesh Kumar Das
2014	—	`conf`	Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. ATS Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman
2014	—	`conf`	Squaring in reversible logic using iterative structure. EWDTS Arindam Banerjee, Debesh Kumar Das
2013	—	`conf`	On Designing Testable Reversible Circuits Using Gate Duplication. VDAT Joyati Mondal, Debesh Kumar Das, Dipak Kumar Kole, Hafizur Rahaman, Bhargab B. Bhattacharya
2013	—	`conf`	The Design of Reversible Multiplier Using Ancient Indian Mathematics. ISED Arindam Banerjee, Debesh Kumar Das
2008	Misc	`conf`	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. VLSI Design Hafizur Rahaman, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya
2004	—	`conf`	Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Asian Test Symposium Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara
2004	J	`jnl`	New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electron. Test. Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
2001	Misc	`conf`	Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
2000	J	`jnl`	Synthesis of symmetric functions for path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya
2000	A	`conf`	Test Generation for Acyclic Sequential Circuits with Hold Registers. ICCAD Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara
1999	—	`conf`	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
1997	Misc	`conf`	New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. VLSI Design Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya
1996	Misc	`conf`	Does retiming affect redundancy in sequential circuits? VLSI Design Debesh Kumar Das, Bhargab B. Bhattacharya
1993	J	`jnl`	Logical redundancies in irredundant combinational circuits. J. Electron. Test. Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya