Debesh K. Das - RankMe

61 papers C 2Misc 7Journal 16Unranked 36

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Fault Testing in AI-Accelerators: A Review. ATS Bhargab B. Bhattacharya, Debesh K. Das, Subhajit Chatterjee, Hafizur Rahaman
2024	J	`jnl`	Power-aware partitioning and test time reduction for 3D-SoC. Innov. Syst. Softw. Eng. Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya, Debesh K. Das
2022	Misc	`conf`	Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. VLSID Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh K. Das, Bhargab B. Bhattacharya
2022	J	`jnl`	Improved Upper Bound on Independent Domination Number for Hypercubes. CoRR Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya
2021	J	`jnl`	An Efficient Design for Testability Approach of Reversible Logic Circuits. J. Circuits Syst. Comput. Joyati Mondal, Arighna Deb, Debesh K. Das
2021	J	`jnl`	Fast algorithms for test optimization of core based 3D SoC. Integr. Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das, Bhargab B. Bhattacharya
2020	—	`conf`	Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing. ATS Tanusree Kaibartta, G. P. Biswas, Debesh K. Das
2019	—	`conf`	Delay Efficient All Optical Carry Lookahead Adder. VDAT Sayantani Roy, Arighna Deb, Debesh K. Das
2019	—	`conf`	Detailed Fault Model for Physical Quantum Circuits. ATS Arighna Deb, Debesh K. Das
2017	—	`conf`	A placement optimization technique for 3D IC. ISED Sabyasachee Banerjee, Subhashis Majumder, Abhishek Varma, Debesh K. Das
2017	J	`jnl`	An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata. Microprocess. Microsystems Arighna Deb, Debesh K. Das
2016	—	`conf`	On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults. ISMVL Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao
2016	J	`jnl`	Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
2015	—	`conf`	An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. ISMVL Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das
2015	C	`conf`	Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. DDECS Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das
2015	—	`conf`	Design-for-testability in reversible logic circuits based on bit-swapping. ATS Joyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya
2015	—	`conf`	Partitioning-based test time reduction for core-based 3DICs. VDAT Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das
2015	—	`conf`	Testing of 3D IC with minimum power using genetic algorithm. IDT Tanusree Kaibartta, Debesh K. Das
2014	—	`conf`	Inadmissible Class of Boolean Functions under Stuck-at Faults. ISMVL Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao
2014	—	`conf`	On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties. ISVLSI Rupali Mitra, Debesh K. Das, Bhargab B. Bhattacharya
2014	—	`conf`	Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. EWDTS Manjari Pradhan, Debesh K. Das, Chandan Giri, Hafizur Rahaman
2014	—	`conf`	Synthesis of Symmetric Boolean Functions Using a Three-Stage Network. ISED Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya
2013	—	`conf`	A design for testability technique for quantum reversible circuits. EWDTS Joyati Mondal, Debesh K. Das, Dipak Kumar Kole, Hafizur Rahaman
2013	J	`jnl`	Derivation of test set for detecting multiple missing-gate faults in reversible circuits. Comput. Electr. Eng. Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2013	J	`jnl`	Inadmissible Class of Boolean Functions under Stuck-at Faults. CoRR Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao
2013	—	`conf`	Modular Design for Symmetric Functions Using Quantum Quaternary Logic. ISED Arighna Deb, Debesh K. Das, Susmita Sur-Kolay
2013	—	`conf`	Optimal stacking of SOCs in a 3D-SIC for post-bond testing. 3DIC Manjari Pradhan, Chandan Giri, Hafizur Rahaman, Debesh K. Das
2013	C	`conf`	Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
2013	—	`conf`	Reversible synthesis of symmetric boolean functions based on unate decomposition. ACM Great Lakes Symposium on VLSI Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya
2012	—	`conf`	Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. ISED Papia Manna, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2011	—	`conf`	Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. ISED Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2011	J	`jnl`	Fault diagnosis in reversible circuits under missing-gate fault model. Comput. Electr. Eng. Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya
2011	—	`conf`	Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman
2010	—	`conf`	Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. Asian Test Symposium Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2009	J	`jnl`	Testable design of AND-EXOR logic networks with universal test sets. Comput. Electr. Eng. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2008	J	`jnl`	An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. IEEE Trans. Instrum. Meas. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2008	—	`conf`	Key Note Speaker. ICIIS Debesh K. Das
2007	—	`conf`	Optimum Test Set for Bridging Fault Detection in Reversible Circuits. ATS Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya
2006	J	`jnl`	Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. J. Electron. Test. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2005	J	`jnl`	A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electron. Test. Biplab K. Sikdar, Samir Roy, Debesh K. Das
2005	—	`conf`	Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ASP-DAC Hafizur Rahaman, Debesh K. Das
2005	Misc	`conf`	Cellular Automata Based Test Structures with Logic Folding. VLSI Design Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das
2005	—	`conf`	Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das
2004	—	`conf`	A Simple Delay Testable Synthesis of Symmetric Functions. AACC Hafizur Rahaman, Debesh K. Das
2004	J	`jnl`	Design & Test Education in Asia. IEEE Des. Test Comput. Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
2004	Misc	`conf`	Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. VLSI Design Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2004	—	`conf`	Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. ASP-DAC Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2003	—	`conf`	Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. Asian Test Symposium Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2002	—	`conf`	A New Synthesis of Symmetric Functions. ASP-DAC/VLSI Design Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2002	J	`jnl`	BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. J. Comput. Sci. Technol. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
2002	—	`conf`	Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. ASP-DAC/VLSI Design Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
2001	—	`conf`	Cellular automata as a built in self test structure. ASP-DAC Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
2001	—	`conf`	Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium Biplab K. Sikdar, Samir Roy, Debesh K. Das
2001	Misc	`conf`	Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. VLSI Design Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly
2000	J	`jnl`	Isomorph-Redundancy in Sequential Circuits. IEEE Trans. Computers Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
1999	—	`conf`	An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ASP-DAC Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
1999	Misc	`conf`	Synthesis of Symmetric Functions for Path-Delay Fault Testability. VLSI Design Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya
1998	Misc	`conf`	Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. VLSI Design Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya
1998	—	`conf`	Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. ASP-DAC Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya
1996	Misc	`conf`	Isomorph-redundancy in sequential circuits. VTS Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
1995	—	`conf`	Testable design of non-scan sequential circuits using extra logic. Asian Test Symposium Debesh K. Das, Bhargab B. Bhattacharya