Debashis Mandal

24 papers A 1C 3Misc 3Journal 13Unranked 4
YearRankTypeTitle / Venue / Authors
2025 C conf
Three-Level Output Side Gate Driver for 1 V Thin-Gate-Oxide NMOSFET Switch in a SIDO Converter.
ISCAS
Abhijit Keshri, Pramit Banerjee, Gautam Dey Kanungo, Kallol Chatterjee, Paras Garg, Santanu Kapat, Debashis Mandal
2024 C conf
A Rail-to-Rail Input Class-AB Linear Amplifier with Improved Bandwidth and Slew-Rate for Envelope Tracking Supply Modulators.
ISCAS
Kondapalli Surya Prasad, Pudi Hemanth, Debashis Mandal
2021 C conf
Towards an Ontology for Enterprise Level Information Security Policy Analysis.
ICISSP
Debashis Mandal, Chandan Mazumdar
2019 J jnl
A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency.
IEEE Trans. Circuits Syst. II Express Briefs
Chengxi Liu, Debashis Mandal, Zhao Yao, Ming Sun, Jim Todsen, Brian Johnson, Sayfe Kiaei, Bertan Bakkaloglu
2019 — conf
A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications.
ISSCC
Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
2019 J jnl
Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time.
IEEE Trans. Circuits Syst. II Express Briefs
Debashis Mandal, Chirag Desai, Bertan Bakkaloglu, Sayfe Kiaei
2019 J jnl
Low-Power/Low-Voltage Integrated CMOS Sense Resistor-Free Analog Power/Current Sensor Compatible With High-Voltage Switching DC-DC Converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shrikant Singh, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
2019 J jnl
Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier.
IEEE J. Solid State Circuits
Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
2018 J jnl
A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters.
ACM Trans. Design Autom. Electr. Syst.
Maryam Shafiee, Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Bertan Bakkaloglu, Sule Ozev
2018 J jnl
Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
Navankur Beohar, Venkata N. K. Malladi, Debashis Mandal, Sule Ozev, Bertan Bakkaloglu
2018 — conf
Sense resistor-free analog power sensor for boost converter with 14.1% gain error and 9.4% offset error.
LASCAS
Shrikant Singh, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
2017 J jnl
A 100-mA, 99.11% Current Efficiency, 2-mV
IEEE Trans. Very Large Scale Integr. Syst.
Michael Cheah, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
2017 J jnl
A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller.
IEEE Trans. Very Large Scale Integr. Syst.
ChaiYong Lim, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei
2017 J jnl
A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error.
IEEE J. Solid State Circuits
Ming Sun, Zhe Yang, Kishan Joshi, Debashis Mandal, Philippe Adell, Bertan Bakkaloglu
2015 Misc conf
Disturbance-free BIST for loop characterization of DC-DC buck converters.
VTS
Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Philippe Adell, Bert Vermeire, Bertan Bakkaloglu, Sule Ozev
2015 A conf
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS.
ISLPED
Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo
2015 J jnl
Prediction of reference spur in frequency synthesisers.
IET Circuits Devices Syst.
Debashis Mandal, Pradip Mandal, T. K. Bhattacharyya
2015 J jnl
Spur reduction in frequency synthesizer with an array of switched capacitors.
Int. J. Circuit Theory Appl.
Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
2014 J jnl
Spur reducing architecture of frequency synthesiser using switched capacitors.
IET Circuits Devices Syst.
Debashis Mandal, Pradip Mandal, T. K. Bhattacharyya
2012 — conf
Spur suppression in frequency synthesizer using switched capacitor array.
ISOCC
Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
2008 J jnl
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design.
J. Comput.
Debashis Mandal, T. K. Bhattacharyya
2007 Misc conf
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer.
VLSI Design
Debashis Mandal, T. K. Bhattacharyya
2006 Misc conf
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor.
VLSI Design
T. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri
2005 — conf
High voltage tolerant output buffer design for mixed voltage interfaces.
ISCAS (5)
Debashis Mandal, Pradip Mandal