Debashis Bhattacharya

22 papers A* 1A 3C 1Misc 6Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2005 J jnl
Transistor-Level Optimization of Digital Designs with Flex Cells.
Computer
Rob Roy, Debashis Bhattacharya, Vamsi Boppana
1999 Misc conf
Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller.
VTS
Debashis Bhattacharya
1998 Misc conf
Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit.
VTS
Debashis Bhattacharya
1997 Misc conf
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients.
VLSI Design
Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
1997 J jnl
Invariance of stereo images via the theory of complex moments.
Pattern Recognit.
Debashis Bhattacharya, Satyabroto Sinha
1997 Misc conf
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit.
VLSI Design
Debashis Bhattacharya, Smith Freeman, Bill Lin
1997 A conf
Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems.
ICCAD
Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
1995 J jnl
A three-stage partial scan design method to ease ATPG.
J. Electron. Test.
Shang-E Tai, Debashis Bhattacharya
1995 J jnl
An efficient method for generating exhaustive test sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ted Stanion, Debashis Bhattacharya, Carl Sechen
1995 J jnl
Test Generation for Path Delay Faults Using Binary Decision Diagrams.
IEEE Trans. Computers
Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
1994 Misc conf
A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph.
VLSI Design
Shang-E Tai, Debashis Bhattacharya
1993 Misc conf
Architecture of a Min-Max Simulator on MARS.
VLSI Design
Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal
1993 A conf
Boolean algebraic test generation using a distributed system.
ICCAD
Debashis Bhattacharya, Prathima Agrawal
1993 C conf
Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph.
ICCD
Shang-E Tai, Debashis Bhattacharya
1992 A* conf
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions.
DAC
Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
1991 — conf
TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation.
FTCS
Ted Stanion, Debashis Bhattacharya
1990 J jnl
A hierarchical test generation methodology for digital circuits.
J. Electron. Test.
Debashis Bhattacharya, John P. Hayes
1990 — conf
Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer.
ISMVL
Debashis Bhattacharya
1990 A conf
CMP3F: a high speed fault simulator for the Connection Machine.
ITC
Ajit Agrawal, Debashis Bhattacharya
1990 J jnl
Designing for high-level test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debashis Bhattacharya, John P. Hayes
1989 J jnl
High-Level Test Generation for VLSI.
Computer
Debashis Bhattacharya, Brian T. Murray, John P. Hayes
1988 — —
Hierarchical modeling and test generation for digital circuits.
Debashis Bhattacharya