Debabrata Mohapatra

23 papers A* 2A 5C 2Misc 2Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2025 A conf
A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint.
DATE
Huseyin Ekin Sumbul, Arne Symons, Lita Yang, Huichu Liu, Tony F. Wu, Matheus Trevisan Moreira, Debabrata Mohapatra, Abhinav Agarwal, Kaushik Ravindran, Chris Thompson, Yuecheng Li, Edith Beigné
2023 — conf
XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.
MLSys
Hyoukjun Kwon, Krishnakumar Nair, Jamin Seo, Jason Yik, Debabrata Mohapatra, Dongyuan Zhan, Jinook Song, Peter Capak, Peizhao Zhang, Peter Vajda, Colby R. Banbury, Mark Mazumder, Liangzhen Lai, Ashish Sirasao, Tushar Krishna, Harshit Khaitan, Vikas Chandra, Vijay Janapa Reddi
2022 J jnl
XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.
CoRR
Hyoukjun Kwon, Krishnakumar Nair, Jamin Seo, Jason Yik, Debabrata Mohapatra, Dongyuan Zhan, Jinook Song, Peter Capak, Peizhao Zhang, Peter Vajda, Colby R. Banbury, Mark Mazumder, Liangzhen Lai, Ashish Sirasao, Tushar Krishna, Harshit Khaitan, Vikas Chandra, Vijay Janapa Reddi
2021 Misc conf
Design Considerations for Edge Neural Network Accelerators: An Industry Perspective.
VLSID
Arnab Raha, Sang Kyun Kim, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Raymond Sung, Cormac Brick, Gautham N. Chinya
2021 C conf
Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices.
ICCD
Arnab Raha, Soumendu Ghosh, Debabrata Mohapatra, Deepak A. Mathaikutty, Raymond Sung, Cormac Brick, Vijay Raghunathan
2014 J jnl
Scalable Effort Hardware Design.
IEEE Trans. Very Large Scale Integr. Syst.
Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
2013 — conf
Energy-efficient recognition and mining processor using scalable effort design.
CICC
Vinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan
2013 — conf
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
CICC
Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim
2013 J jnl
Low-Power Digital Signal Processing Using Approximate Adders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy
2012 J jnl
Empirical Evidence Against CAPM: Relating Alphas and Returns to Betas.
IEEE J. Sel. Top. Signal Process.
Mayur Agrawal, Debabrata Mohapatra, Ilya Pollak
2012 J jnl
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems.
J. Signal Process. Syst.
Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2011 J jnl
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol.
Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2011 A conf
Design of voltage-scalable meta-functions for approximate computing.
DATE
Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy
2011 Misc conf
Empirical evidence against CAPM: Relating alphas and returns to betas.
ICASSP
Mayur Agrawal, Debabrata Mohapatra, Ilya Pollak
2011 A conf
IMPACT: imprecise adders for low-power approximate computing.
ISLPED
Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy
2011 — conf
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays.
ASP-DAC
Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy
2010 A* conf
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
DAC
Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar
2010 C conf
VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture.
ICCD
Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2010 J jnl
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst.
Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
2009 A* conf
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
DAC
Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2009 A conf
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.
ISLPED
Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
2009 — conf
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.
SiPS
Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2007 A conf
Low-power process-variation tolerant arithmetic units using input-based elastic clocking.
ISLPED
Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy