Dean L. Lewis - RankMe

12 papers A* 1A 2C 1Journal 2Unranked 5

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2012	—	`conf`	3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2012	—	`—`	Design for pre-bond testability in 3D integrated circuits. Dean L. Lewis
2011	C	`conf`	Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. ICCD Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee
2011	J	`jnl`	Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
2010	A*	`conf`	An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. HPCA Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee
2010	—	`conf`	Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2009	—	`conf`	Architectural evaluation of 3D stacked RRAM caches. 3DIC Dean L. Lewis, Hsien-Hsin S. Lee
2009	—	`conf`	High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. ISVLSI Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee
2009	A	`conf`	Pre-bond testable low-power clock tree design for 3D stacked ICs. ICCAD Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
2009	—	`conf`	Testing Circuit-Partitioned 3D IC Designs. ISVLSI Dean L. Lewis, Hsien-Hsin S. Lee
2007	A	`conf`	A scanisland based design enabling prebond testability in die-stacked microprocessors. ITC Dean L. Lewis, Hsien-Hsin S. Lee