Dawei Ye

21 papers C 4Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
Analysis and Design of a Series-Resonance VCO With Magnetic Mutual Resistance.
IEEE J. Solid State Circuits
Luyang Chen, Dawei Ye
2023 J jnl
Echo State Network-Enabled Intelligent Smart Sensor Design for Creating a Robotic Nervous System.
Int. J. Pattern Recognit. Artif. Intell.
Dawei Ye, Bingxin Cao, Weiping Zhou
2022 — conf
A 0.021mm
ISSCC
Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi
2022 J jnl
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction.
Integr.
Rongjin Xu, Dawei Ye, Chuanjin Richard Shi
2022 J jnl
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rongjin Xu, Dawei Ye, Chuanjin Richard Shi
2022 J jnl
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain".
IEEE J. Solid State Circuits
Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2021 J jnl
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain.
IEEE J. Solid State Circuits
Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2021 — conf
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference.
A-SSCC
Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, Chuanjin Richard Shi
2021 — conf
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording.
CICC
Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, Chuanjin Richard Shi
2020 J jnl
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst.
Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi
2020 C conf
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
ISCAS
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi
2020 J jnl
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, Chuanjin Richard Shi
2020 J jnl
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation.
IEEE J. Solid State Circuits
Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, Chuanjin Richard Shi
2019 C conf
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
ISCAS
Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi
2019 — conf
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity.
ISSCC
Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2019 C conf
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply.
ISCAS
Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi
2018 — conf
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.
ISSCC
Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, Chuanjin Richard Shi
2016 — conf
26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience.
ISSCC
Dawei Ye, Ronan A. R. van der Zee, Bram Nauta
2016 J jnl
A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance.
IEEE J. Solid State Circuits
Dawei Ye, Ronan A. R. van der Zee, Bram Nauta
2013 C conf
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing.
ISCAS
Dawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee
2011 — conf
A 0.13µm CMOS ΔΣ PLL FM transmitter.
NORCHIP
Ying Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland