Davor Capalija

15 papers A 2B 3Misc 3Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Panel: HotI 2025.
HOTI
Peter Olcott, Phil Brown, Davor Capalija, Ethan Lockshin, Sid Sheth
2024 — conf
Blackhole & TT-Metalium: The Standalone AI Computer and its Programming Model.
HCS
Jasmina Vasiljevic, Davor Capalija
2021 J jnl
Compute Substrate for Software 2.0.
IEEE Micro
Jasmina Vasiljevic, Ljubisa Bajic, Davor Capalija, Stanislav Sokorac, Dragoljub Ignjatovic, Lejla Bajic, Milos Trajkovic, Ivan Hamer, Ivan Matosevic, Aleksandar Cejkov, Utku Aydonat, Tony Zhou, Syed Zohaib Gilani, Armond Paiva, Joseph Chu, Djordje Maksimovic, Stephen Alexander Chin, Zahi Moudallal, Akhmed Rakhmati, Sean Nijjar, Almeet Bhullar, Boris Drazic, Charles Lee, James Sun, Kei-Ming Kwong, James Connolly, Miles Dooley, Hassan Farooq, Joy Yu Ting Chen, Matthew Walker, Keivan Dabiri, Kyle Mabee, Rakesh Shaji Lal, Namal Rajatheva, Renjith Retnamma, Shripad Karodi, Daniel Rosen, Emilio Munoz, Andrew Lewycky, Aleksandar Knezevic, Raymond Kim, Allan Rui, Alexander Drouillard, David Thompson
2018 — conf
Flexibility: FPGAs and CAD in Deep Learning Acceleration.
ISPD
Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah
2018 A conf
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
FPGA
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018 B conf
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
FPL
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2017 J jnl
An OpenCL(TM) Deep Learning Accelerator on Arria 10.
CoRR
Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
2017 A conf
An OpenCL™ Deep Learning Accelerator on Arria 10.
FPGA
Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
2017 — conf
Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.
IWOCL
Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu
2017 — conf
Customizable FPGA OpenCL matrix multiply design template for deep neural networks.
FPT
Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra
2014 B conf
Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays.
FPL
Davor Capalija, Tarek S. Abdelrahman
2013 B conf
A high-performance overlay architecture for pipelined execution of data flow graphs.
FPL
Davor Capalija, Tarek S. Abdelrahman
2013 J jnl
Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor.
IEEE Trans. Parallel Distributed Syst.
Davor Capalija, Tarek S. Abdelrahman
2011 Misc conf
Towards Synthesis-Free JIT Compilation to Commodity FPGAs.
FCCM
Davor Capalija, Tarek S. Abdelrahman
2006 Misc conf
A Multithreaded Soft Processor for SoPC Area Reduction.
FCCM
Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown