Davide Zoni - RankMe

93 papers A 7C 12Misc 1Journal 42Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support. ACM Comput. Surv. Giovanni Agosta, Andrea Galimberti, Davide Zoni
2026	J	`jnl`	FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration. IEEE Trans. Very Large Scale Integr. Syst. Gabriele Montanaro, Francesco Trovò, Davide Zoni
2026	J	`jnl`	OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation. CoRR Giuseppe Chiari, Michele Piccoli, Davide Zoni
2026	J	`jnl`	Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs. IEEE Trans. Computers Gabriele Montanaro, Andrea Galimberti, Davide Zoni
2025	C	`conf`	A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs. ISCAS Andrea Galimberti, Gabriele Montanaro, Andrea Motta, Federico Proverbio, Davide Zoni
2025	J	`jnl`	A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs. CoRR Andrea Galimberti, Gabriele Montanaro, Andrea Motta, Federico Proverbio, Davide Zoni
2025	J	`jnl`	A Deep Learning-Assisted Template Attack Against Dynamic Frequency Scaling Countermeasures. IEEE Trans. Computers Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni
2025	—	`conf`	A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA. ASYNC Giuseppe Chessa, Elena Bellodi, Michele Favalli, Davide Zoni, Davide Bertozzi
2025	J	`jnl`	An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research. IEEE Trans. Computers Davide Zoni, Andrea Galimberti, Davide Galli
2025	J	`jnl`	Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis. IACR Trans. Cryptogr. Hardw. Embed. Syst. Davide Galli, Giuseppe Chiari, Davide Zoni
2025	C	`conf`	FARMER: An Online-Learning Driven Methodology for Workload Consolidation on Large FPGAs. ISCAS Gabriele Montanaro, Francesco Trovò, Davide Zoni
2025	C	`conf`	Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability. DSD Giovanni Agosta, Enrico Bini, Davide Baroffio, Carlo Brandolese, Michele Castrovilli, Daniele Cattaneo, Daniele Cesarini, William Fornaciari, Andrea Galimberti, Alberto Garfagnini, Arsenii Gavrikov, Francesco Iannone, Marco Lapegna, Tomas Antonio Lopez, Gabriele Magnani, Gabriele Mencagli, Cecilia Metra, Martin Eugenio Omana, Filippo Palombi, Federico Reghenzani, Josie E. Rodriguez Condia, A. Serafini, Matteo Sonza Reorda, Davide Zoni, Giuseppe Zummo
2025	—	`conf`	Performance Implications at the Intersection of AF_XDP and Programmable NICs. eBPF@SIGCOMM Marco Molè, Farbod Shahinfar, Francesco Maria Tranquillo, Davide Zoni, Aurojit Panda, Gianni Antichi
2025	C	`conf`	Rabbit: Dynamic Clock Randomization to Protect against Side-Channel Attacks. ISCAS Davide Galli, Matteo Matteucci, Davide Zoni
2025	A	`conf`	Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems. ICCAD Davide Zoni, Andrea Galimberti, Adriano Guarisco
2025	J	`jnl`	Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems. CoRR Davide Zoni, Andrea Galimberti, Adriano Guarisco
2024	A	`conf`	A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. DATE Giuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni
2024	J	`jnl`	A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. CoRR Giuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni
2024	C	`conf`	A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS. ICCD Gabriele Montanaro, Andrea Galimberti, Davide Zoni
2024	J	`jnl`	A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS. CoRR Gabriele Montanaro, Andrea Galimberti, Davide Zoni
2024	—	`conf`	A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits. ISQED Teo Vallone, Hayri Verner Hasou, Ernesto Colizzi, Sara Vinco, Davide Zoni
2024	J	`jnl`	An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research. CoRR Davide Zoni, Andrea Galimberti, Davide Galli
2024	J	`jnl`	Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms. CoRR Andrea Galimberti, Michele Piccoli, Davide Zoni
2024	J	`jnl`	Design-time methodology for optimizing mixed-precision CPU architectures on FPGA. J. Syst. Archit. Lev Denisov, Andrea Galimberti, Daniele Cattaneo, Giovanni Agosta, Davide Zoni
2024	J	`jnl`	Functional ISS-Driven Verification of Superscalar RISC-V Processors. CoRR Andrea Galimberti, Marco Vitali, Sebastiano Vittoria, Davide Zoni
2024	J	`jnl`	Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces Using Deep-Learning. CoRR Davide Galli, Giuseppe Chiari, Davide Zoni
2024	C	`conf`	Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning. ICCD Davide Galli, Giuseppe Chiari, Davide Zoni
2024	Misc	`conf`	Rethinking the Switch Architecture for Stateful In-network Computing. HotNets Alberto Lerner, Davide Zoni, Paolo Costa, Gianni Antichi
2024	J	`jnl`	The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs. CoRR Davide Galli, Adriano Guarisco, William Fornaciari, Matteo Matteucci, Davide Zoni
2024	C	`conf`	The TEXTAROSSA Project: Cool all the Way Down to the Hardware. DSD Antonio Filgueras, Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Pasqua D'Ambra, Massimo Bernaschi, Andrea Biagioni, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Carlotta Chiarini, Francesca Lo Cicero, Paolo Cretaro, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Juan Miguel De Haro Ruiz, Francesco Iannone, Daniel Jaschke, Daniel Jiménez-González, Michal Kulczewski, Alberto Leva, Alessandro Lonardo, Michele Martinelli, Xavier Martorell, Simone Montangero, Lucas Morais, Ariel Oleksiak, Paolo Palazzari, Luca Pontisso, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Carlo Saverio Lodi, Francesco Simula, Federico Terraneo, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo
2023	J	`jnl`	A Survey on Run-time Power Monitors at the Edge. ACM Comput. Surv. Davide Zoni, Andrea Galimberti, William Fornaciari
2023	—	`conf`	An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE. PARMA-DITAM Andrea Galimberti, Gabriele Montanaro, William Fornaciari, Davide Zoni
2023	—	`conf`	Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments. PARMA-DITAM Michele Piccoli, Davide Zoni, William Fornaciari, Giuseppe Massari, Marco Cococcioni, Federico Rossi, Sergio Saponara, Emanuele Ruffaldi
2023	—	`conf`	HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs. ICECS Andrea Galimberti, Gabriele Montanaro, Davide Zoni
2023	A	`conf`	Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems. DATE William Fornaciari, Giovanni Agosta, Daniele Cattaneo, Lev Denisov, Andrea Galimberti, Gabriele Magnani, Davide Zoni
2023	—	`conf`	RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. SAMOS William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa
2022	J	`jnl`	An Evaluation of the State-of-the-Art Software and Hardware Implementations of BIKE. CoRR Andrea Galimberti, Gabriele Montanaro, William Fornaciari, Davide Zoni
2022	J	`jnl`	Cost-effective fixed-point hardware support for RISC-V embedded systems. J. Syst. Archit. Davide Zoni, Andrea Galimberti
2022	J	`jnl`	Design of Side-Channel-Resistant Power Monitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Davide Zoni, Luca Cremona, William Fornaciari
2022	J	`jnl`	Efficient and Scalable FPGA Design of GF($2^m$2m) Inversion for Post-Quantum Cryptosystems. IEEE Trans. Computers Andrea Galimberti, Gabriele Montanaro, Davide Zoni
2022	C	`conf`	FPGA implementation of BIKE for quantum-resistant TLS. DSD Andrea Galimberti, Davide Galli, Gabriele Montanaro, William Fornaciari, Davide Zoni
2022	J	`jnl`	Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. J. Syst. Archit. Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni
2022	—	`conf`	Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators. ICECS 2022 Gabriele Montanaro, Andrea Galimberti, Ernesto Colizzi, Davide Zoni
2022	J	`jnl`	Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators. CoRR Gabriele Montanaro, Andrea Galimberti, Ernesto Colizzi, Davide Zoni
2022	—	`conf`	On the Effectiveness of True Random Number Generators Implemented on FPGAs. SAMOS Davide Galli, Andrea Galimberti, William Fornaciari, Davide Zoni
2022	—	`conf`	On the use of hardware accelerators in QC-MDPC code-based cryptography. CF Andrea Galimberti, Davide Galli, Gabriele Montanaro, William Fornaciari, Davide Zoni
2022	J	`jnl`	Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach. Microprocess. Microsystems Giovanni Agosta, Marco Aldinucci, Carlos Álvarez, Roberto Ammendola, Yasir Arfat, Olivier Beaumont, Massimo Bernaschi, Andrea Biagioni, Tommaso Boccali, Bérenger Bramas, Carlo Brandolese, Barbara Cantalupo, Mauro Carrozzo, Daniele Cattaneo, Alessandro Celestini, Massimo Celino, Iacopo Colonnelli, Paolo Cretaro, Pasqua D'Ambra, Marco Danelutto, Roberto Esposito, Lionel Eyraud-Dubois, Antonio Filgueras, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Brice Goglin, Daniele Gregori, Abdou Guermouche, Francesco Iannone, Michal Kulczewski, Francesca Lo Cicero, Alessandro Lonardo, Alberto Riccardo Martinelli, Michele Martinelli, Xavier Martorell, Giuseppe Massari, Simone Montangero, Gianluca Mittone, Raymond Namyst, Ariel Oleksiak, Paolo Palazzari, Pier Stanislao Paolucci, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Francesco Simula, Federico Terraneo, Samuel Thibault, Massimo Torquati, Matteo Turisini, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo
2021	J	`jnl`	An FPU design template to optimize the accuracy-efficiency-area trade-off. Sustain. Comput. Informatics Syst. Davide Zoni, Andrea Galimberti, William Fornaciari
2021	J	`jnl`	Automatic identification and hardware implementation of a resource-constrained power model for embedded systems. Sustain. Comput. Informatics Syst. Luca Cremona, William Fornaciari, Davide Zoni
2021	C	`conf`	TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale. DSD Giovanni Agosta, Daniele Cattaneo, William Fornaciari, Andrea Galimberti, Giuseppe Massari, Federico Reghenzani, Federico Terraneo, Davide Zoni, Carlo Brandolese, Massimo Celino, Francesco Iannone, Paolo Palazzari, Giuseppe Zummo, Massimo Bernaschi, Pasqua D'Ambra, Sergio Saponara, Marco Danelutto, Massimo Torquati, Marco Aldinucci, Yasir Arfat, Barbara Cantalupo, Iacopo Colonnelli, Roberto Esposito, Alberto Riccardo Martinelli, Gianluca Mittone, Olivier Beaumont, Bérenger Bramas, Lionel Eyraud-Dubois, Brice Goglin, Abdou Guermouche, Raymond Namyst, Samuel Thibault, Antonio Filgueras, Miquel Vidal, Carlos Álvarez, Xavier Martorell, Ariel Oleksiak, Michal Kulczewski, Alessandro Lonardo, Piero Vicini, Francesca Lo Cicero, Francesco Simula, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Pier Stanislao Paolucci, Matteo Turisini, Francesco Giacomini, Tommaso Boccali, Simone Montangero, Roberto Ammendola
2020	J	`jnl`	All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores. IEEE Trans. Computers Davide Zoni, Luca Cremona, William Fornaciari
2020	J	`jnl`	All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs. IEEE Embed. Syst. Lett. Davide Zoni, Luca Cremona, William Fornaciari
2020	J	`jnl`	Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography. IEEE Access Davide Zoni, Andrea Galimberti, William Fornaciari
2020	J	`jnl`	Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials. IEEE Access Davide Zoni, Andrea Galimberti, William Fornaciari
2020	—	`conf`	Integrating Side Channel Security in the FPGA Hardware Design Flow. COSADE Alessandro Barenghi, Matteo Brevi, William Fornaciari, Gerardo Pelosi, Davide Zoni
2020	J	`jnl`	Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alessandro Barenghi, William Fornaciari, Gerardo Pelosi, Davide Zoni
2020	—	`conf`	VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications. SAMOS Luca Cremona, William Fornaciari, Andrea Galimberti, Andrea Romanoni, Davide Zoni
2019	—	`conf`	Analysis and countermeasures to side-channel attacks: a hardware design perspective. ReCoSoC Davide Zoni
2019	—	`conf`	Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions. ICECS Alessandro Barenghi, William Fornaciari, Andrea Galimberti, Gerardo Pelosi, Davide Zoni
2019	C	`conf`	Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs. PDP Tamer Ahmed Eltaras, William Fornaciari, Davide Zoni
2018	J	`jnl`	A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture. ACM Trans. Design Autom. Electr. Syst. Davide Zoni, Alessandro Barenghi, Gerardo Pelosi, William Fornaciari
2018	J	`jnl`	DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks. ACM Trans. Archit. Code Optim. Davide Zoni, Luca Colombo, William Fornaciari
2018	J	`jnl`	Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
2018	—	`conf`	Fast Estimations of Failure Probability Over Long Time Spans. NANOARCH Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos, Dimitrios Rodopoulos, Francky Catthoor, Yiannakis Sazeides, Davide Zoni, Dimitrios Soudris
2018	A	`conf`	PowerProbe: Run-time power modeling through automatic RTL instrumentation. DATE Davide Zoni, Luca Cremona, William Fornaciari
2018	J	`jnl`	PowerTap: All-digital power meter modeling for run-time power monitoring. Microprocess. Microsystems Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari
2018	—	`conf`	Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farrés, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
2018	—	`conf`	Towards Fine-Grained DVFS in Embedded Multi-core CPUs. ARCS Giuseppe Massari, Federico Terraneo, Michele Zanella, Davide Zoni
2017	J	`jnl`	BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. J. Parallel Distributed Comput. Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yiannakis Sazeides
2017	J	`jnl`	CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia
2017	—	`conf`	DENA: A DVFS-Capable Heterogeneous NoC Architecture. ISVLSI Luca Cremona, William Fornaciari, Andrea Marchese, Michele Zanella, Davide Zoni
2017	C	`conf`	MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni
2016	J	`jnl`	A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations. J. Signal Process. Syst. Davide Zoni, Federico Terraneo, William Fornaciari
2016	J	`jnl`	CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. IEEE Trans. Parallel Distributed Syst. Davide Zoni, José Flich, William Fornaciari
2016	A	`conf`	Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni
2015	J	`jnl`	A control-based methodology for power-performance optimization in NoCs exploiting DVFS. J. Syst. Archit. Davide Zoni, Federico Terraneo, William Fornaciari
2015	—	`conf`	An accurate simulation framework for thermal explorations and optimizations. RAPIDO@HiPEAC Federico Terraneo, Davide Zoni, William Fornaciari
2015	J	`jnl`	Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. ACM J. Emerg. Technol. Comput. Syst. Davide Zoni, William Fornaciari
2015	C	`conf`	TEST: Assessing NoC Policies Facing Aging and Leakage Power. DSD Davide Zoni, Luca Borghese, Giuseppe Massari, Simone Libutti, William Fornaciari
2015	—	`conf`	The MANGO FET-HPC Project: An Overview. CSE José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni
2014	—	`—`	Exploring power reliability and performance aspects in on-chip networks for multi-cores. Davide Zoni
2013	—	`conf`	A cycle accurate simulation framework for asynchronous NoC design. ISSoC Federico Terraneo, Davide Zoni, William Fornaciari
2013	—	`conf`	Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. PATMOS Davide Zoni, José Flich, William Fornaciari
2013	—	`conf`	An analytical, dynamic, power-performance router model for run-time NoC optimizations. SoCC Davide Zoni, Federico Terraneo, William Fornaciari
2013	—	`conf`	NBTI-aware design of NoC buffers. INA-OCMC@HiPEAC Davide Zoni, William Fornaciari
2013	A	`conf`	Sensor-wise methodology to face NBTI stress of NoC buffers. DATE Davide Zoni, William Fornaciari
2012	—	`conf`	A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures. ARCS Davide Zoni, Patrick Bellasi, William Fornaciari
2012	—	`conf`	A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures. ISVLSI Simone Corbetta, Davide Zoni, William Fornaciari
2012	—	`conf`	A sensor-less NBTI mitigation methodology for NoC architectures. SoCC Davide Zoni, William Fornaciari
2012	—	`conf`	Consolidation of multi-tier workloads with performance and reliability constraints. HPCS Andrea Sansottera, Davide Zoni, Paolo Cremonesi, William Fornaciari
2012	A	`conf`	HANDS: heterogeneous architectures and networks-on-chip design and simulation. ISLPED Davide Zoni, Simone Corbetta, William Fornaciari
2012	—	`conf`	Thermal/performance trade-off in network-on-chip architectures. ISSoC Davide Zoni, Simone Corbetta, William Fornaciari
2012	—	`conf`	Towards energy-efficient functional configuration in WSNs. PDeS Carlo Brandolese, William Fornaciari, Luigi Rucco, Davide Zoni