Davide Sacchetto

15 papers A* 1A 3C 4Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2022 — conf
Hybrid InP-SiN microring-resonator based tunable laser with high output power and narrow linewidth for high capacity coherent systems.
OFC
Cosimo Calò, Kaoutar Benyahya, Haïk Mardoyan, Philippe Charbonnier, Davide Sacchetto, Michael Zervas, Karim Mekhazni, Delphine Lanteri, Harry Gariah, Catherine Fortin, Nicolas Vaissière, Antoine Elias, Olivier Parillaud, Franck Mallecot, Jean Decobert, Frédéric Pommereau, Jérémie Renaudier
2019 — ch.
Memory Effects in Multi-terminal Solid State Devices and Their Applications.
Handbook of Memristor Networks
Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli
2016 J jnl
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici
2015 A conf
A ultra-low-power FPGA based on monolithically integrated RRAMs.
DATE
Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2015 C conf
Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology.
ISCAS
Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici
2014 J jnl
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli
2013 — conf
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
NEWCAS
Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli
2013 A* conf
Towards structured ASICs using polarity-tunable Si nanowire transistors.
DAC
Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2013 A conf
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
DATE
Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2012 C conf
GMS: Generic memristive structure for non-volatile FPGAs.
VLSI-SoC
Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli
2012 J jnl
Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.
Proc. IEEE
Davide Sacchetto, Giovanni De Micheli, Yusuf Leblebici
2012 — conf
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
NANOARCH
Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2011 A conf
Alternative design methodologies for the next generation logic switch.
ICCAD
Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici
2010 C conf
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.
ISCAS
Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici
2010 C conf
Memristive devices fabricated with silicon nanowire schottky barrier transistors.
ISCAS
Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici