Davide Rossi - RankMe

234 papers A* 2A 20C 17Misc 1Journal 133Unranked 61

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions. CoRR Simone Manoni, Emanuele Parisi, Riccardo Tedeschi, Davide Rossi, Andrea Acquaviva, Andrea Bartolini
2026	J	`jnl`	Temporal Lockstep: Low-Cost Resilient Design for Microcontroller-Class RISC-V Processors. IEEE Access Riccardo Tedeschi, Alessandro Nadalini, Yvan Tortorella, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Luca Benini, Davide Rossi
2025	J	`jnl`	A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU. IEEE J. Emerg. Sel. Topics Circuits Syst. Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. CoRR Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. CoRR Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025	J	`jnl`	AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. IEEE Trans. Computers Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025	J	`jnl`	CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. CoRR Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart, Nils Wistoff, Zexin Fu, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Jean-Baptiste Rigaud, Olivier Potin, Jean-Roch Coulon, César Fuguet, Luca Benini, Davide Rossi
2025	J	`jnl`	Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors. CoRR Alessandro Ottaviano, Andrino Meli, Paul Scheffler, Giovanni Bambini, Robert Balas, Davide Rossi, Andrea Bartolini, Luca Benini
2025	C	`conf`	Exploring MRAM for On-Chip Texture Storage in Rendering Applications. VLSI-SoC Nicolás Villegas, Stefano Romanini, Moritz Scherer, Warren Hunt, Syed Shakib Sarwar, Barbara De Salvo, Chiao Liu, Francesco Conti, Davide Rossi, Luca Benini, Jorge Gomez
2025	—	`conf`	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. CF Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi
2025	J	`jnl`	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. CoRR Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi
2025	—	`conf`	HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCs. ISVLSI Luigi Ghionda, Riccardo Tedeschi, Yvan Tortorella, Arpan Suravi Prasad, Davide Rossi, Luca Benini, Francesco Conti
2025	J	`jnl`	Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-core Computing Clusters for Reliable Processing in Space. ACM Trans. Cyber Phys. Syst. Michael Rogenmoser, Yvan Tortorella, Davide Rossi, Francesco Conti, Luca Benini
2025	J	`jnl`	Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. CoRR Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025	J	`jnl`	Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi
2025	J	`jnl`	Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. IEEE J. Solid State Circuits Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. CoRR Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	C	`conf`	PACE-Lite: Compact and Efficient Piecewise Polynomial Approximation for Transformer Nonlinearity Acceleration. ICCD Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini
2025	—	`conf`	PACE: An Optimal Piecewise Polynomial Approximation Unit for Flexible and Efficient Transformer Non-linearity Acceleration. ISVLSI Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini
2025	J	`jnl`	Parallelization is All System Identification Needs: End-to-End Vibration Diagnostics on a Multicore RISC-V Edge Device. IEEE Internet Things J. Amirhossein Kiamarzi, Amirhossein Moallemi, Federica Zonzini, Davide Brunelli, Davide Rossi, Giuseppe Tagliavini
2025	—	`conf`	Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution. CF Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini
2025	J	`jnl`	Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution. CoRR Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini
2025	A	`conf`	SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate Exponentiation. DATE Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2025	C	`conf`	Towards RISC-V-based HPC: The Italian Pathfinding Activities in the DARE-SGA1 Project. DSD Giovanni Agosta, Marco Aldinucci, Andrea Bartolini, Laura Bellentani, Andrea Biagioni, Daniele Cesarini, Carlotta Chiarini, Iacopo Colonnelli, Pietro Delugas, Lev Denisov, Ottorino Frezza, Marco Grangetto, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Andrea Maslov, Mauro Olivieri, Pierpaolo Perticaroli, Luca Pontisso, Cristian Rossi, Davide Rossi, Sergio Saponara, Antonio Sciarappa, Francesco Simula, Matteo Sonza Reorda, Massimo Torquati, Piero Vicini
2025	A	`conf`	Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring. DATE Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi
2025	J	`jnl`	Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring. CoRR Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi
2025	J	`jnl`	Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. ACM Trans. Embed. Comput. Syst. Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi
2024	J	`jnl`	A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU. CoRR Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2024	—	`conf`	A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. CF (Companion) Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi
2024	J	`jnl`	A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. CoRR Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi
2024	J	`jnl`	A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. IEEE Trans. Circuits Syst. I Regul. Pap. Luca Valente, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
2024	J	`jnl`	A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation. CoRR Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi
2024	—	`conf`	Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips. CF Emanuele Parisi, Alberto Musa, Maicol Ciani, Francesco Barchi, Davide Rossi, Andrea Bartolini, Andrea Acquaviva
2024	J	`jnl`	Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips. CoRR Emanuele Parisi, Alberto Musa, Maicol Ciani, Francesco Barchi, Davide Rossi, Andrea Bartolini, Andrea Acquaviva
2024	J	`jnl`	ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. Int. J. Parallel Program. Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini
2024	J	`jnl`	Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. CoRR Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi
2024	J	`jnl`	Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. WiPiEC Journal Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi
2024	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE J. Solid State Circuits Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2024	—	`conf`	Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024	J	`jnl`	Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024	J	`jnl`	Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience. CoRR Francesco Conti, Angelo Garofalo, Davide Rossi, Giuseppe Tagliavini, Luca Benini
2024	—	`conf`	QR-PULP: Streamlining QR Decomposition for RISC-V Parallel Ultra-Low-Power Platforms. CF Amirhossein Kiamarzi, Davide Rossi, Giuseppe Tagliavini
2024	J	`jnl`	Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine. IEEE J. Solid State Circuits Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2024	—	`conf`	Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. ASAP Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
2024	J	`jnl`	Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. CoRR Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini
2024	J	`jnl`	TOP: Towards Open & Predictable Heterogeneous SoCs. CoRR Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini
2024	J	`jnl`	TOP: Towards Open & Predictable Heterogeneous SoCs. IEEE Trans. Computers Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini
2024	A	`conf`	TitanCFI: Toward Enforcing Control-Flow Integrity in the Root -of- Trust. DATE Emanuele Parisi, Alberto Musa, Simone Manoni, Maicol Ciani, Davide Rossi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva
2024	J	`jnl`	TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust. CoRR Emanuele Parisi, Alberto Musa, Simone Manoni, Maicol Ciani, Davide Rossi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva
2024	J	`jnl`	Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. CoRR Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi
2023	—	`conf`	A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. ISSCC Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
2023	—	`conf`	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. ISVLSI Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. CoRR Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration. CoRR Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto
2023	J	`jnl`	CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration. IEEE Trans. Very Large Scale Integr. Syst. Bruno Sá, Luca Valente, José Martins, Davide Rossi, Luca Benini, Sandro Pinto
2023	J	`jnl`	ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. CoRR Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini
2023	C	`conf`	Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case. ISCAS Maicol Ciani, Stefano Bonato, Rafail Psiakis, Angelo Garofalo, Luca Valente, Suresh Sugumar, Alessandro Giusti, Davide Rossi, Daniele Palossi
2023	J	`jnl`	Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case. CoRR Maicol Ciani, Stefano Bonato, Rafail Psiakis, Angelo Garofalo, Luca Valente, Suresh Sugumar, Alessandro Giusti, Davide Rossi, Daniele Palossi
2023	J	`jnl`	DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. CoRR Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. IEEE Trans. Circuits Syst. I Regul. Pap. Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2023	C	`conf`	ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I ISCAS Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. CoRR Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023	A	`conf`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. DATE Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2023	J	`jnl`	Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Binyamin Frankel, Eyal Sarfati, Davide Rossi, Shmuel Wimer
2023	J	`jnl`	Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors. IEEE Wirel. Commun. Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Joshua Alexander Harrison Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
2023	A	`conf`	HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. DATE Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi
2023	J	`jnl`	Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space. CoRR Michael Rogenmoser, Yvan Tortorella, Davide Rossi, Francesco Conti, Luca Benini
2023	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. CoRR Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2023	A*	`conf`	PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
2023	J	`jnl`	PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst
2023	J	`jnl`	RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration. CoRR Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration. Future Gener. Comput. Syst. Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti
2023	C	`conf`	Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU. DSD Gianmarco Ottavi, Florian Zaruba, Luca Benini, Davide Rossi
2023	J	`jnl`	Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. CoRR Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2023	J	`jnl`	Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. IEEE Trans. Very Large Scale Integr. Syst. Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2023	—	`conf`	Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi
2023	J	`jnl`	Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine. CoRR Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2023	—	`conf`	Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS. ESSCIRC Moritz Scherer, Manuel Eggimann, Alfio Di Mauro, Arpan Suravi Prasad, Francesco Conti, Davide Rossi, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2023	A	`conf`	TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. DATE Seyed Ahmad Mirsalari, Giuseppe Tagliavini, Davide Rossi, Luca Benini
2022	J	`jnl`	A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks. CoRR Angelo Garofalo, Gianmarco Ottavi, Francesco Conti, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Angelo Garofalo, Gianmarco Ottavi, Francesco Conti, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. IEEE Trans. Parallel Distributed Syst. Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
2022	—	`conf`	ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration. SAMOS Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini
2022	—	`conf`	Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. ESSCIRC Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2022	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2022	J	`jnl`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. CoRR Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2022	J	`jnl`	HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. CoRR Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi
2022	—	`conf`	Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs. HCS Alfio Di Mauro, Moritz Scherer, Davide Rossi, Luca Benini
2022	J	`jnl`	Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs. CoRR Alfio Di Mauro, Moritz Scherer, Davide Rossi, Luca Benini
2022	A	`conf`	RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. DATE Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti
2022	J	`jnl`	RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs. CoRR Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti
2022	—	`conf`	Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. AICAS Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	—	`conf`	4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	J	`jnl`	A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL. IEEE Trans. Circuits Syst. II Express Briefs Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
2021	—	`conf`	A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. ESSCIRC Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2021	J	`jnl`	A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
2021	J	`jnl`	A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. CoRR Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
2021	J	`jnl`	Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. IEEE Trans. Very Large Scale Integr. Syst. Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis
2021	—	`conf`	Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF Joshua Alexander Harrison Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal
2021	J	`jnl`	Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. IEEE Trans. Very Large Scale Integr. Syst. Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
2021	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. IEEE Trans. Computers Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2021	—	`conf`	End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? AICAS Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2021	J	`jnl`	End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? CoRR Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2021	J	`jnl`	Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. IEEE Trans. Parallel Distributed Syst. Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
2021	C	`conf`	GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ICCD Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	C	`conf`	Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors. VLSI-SoC Luca Valente, Davide Rossi, Luca Benini
2021	—	`conf`	Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. ARCS Fabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini
2021	J	`jnl`	Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. IEEE Trans. Emerg. Top. Comput. Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	C	`conf`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ARITH Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL. CoRR Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
2020	J	`jnl`	A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Renzini, Claudio Mucci, Davide Rossi, Eleonora Franchi Scarselli, Roberto Canegallo
2020	—	`conf`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ISVLSI Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A custom processor for protocol-independent packet parsing. Microprocess. Microsystems Hesam Zolfaghari, Davide Rossi, Jari Nurmi
2020	J	`jnl`	A transprecision floating-point cluster for efficient near-sensor data analytics. CoRR Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
2020	J	`jnl`	Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node. CoRR Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
2020	J	`jnl`	Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node. IEEE Trans. Circuits Syst. Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
2020	C	`conf`	An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. ISCAS Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
2020	J	`jnl`	An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. CoRR Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
2020	J	`jnl`	Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes. CoRR Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
2020	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. CoRR Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2020	J	`jnl`	Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices. CoRR Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	—	`conf`	Enabling mixed-precision quantized neural networks in extreme-edge devices. CF Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	J	`jnl`	Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. CoRR Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
2020	A	`conf`	Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster. DATE Jie Chen, Igor Loi, Luca Benini, Davide Rossi
2020	J	`jnl`	Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge. IEEE Embed. Syst. Lett. Paolo Meloni, Daniela Loi, Gianfranco Deriu, Marco Carreras, Francesco Conti, Alessandro Capotondi, Davide Rossi
2020	J	`jnl`	Flexible Software-Defined Packet Processing Using Low-Area Hardware. IEEE Access Hesam Zolfaghari, Davide Rossi, Walter Cerroni, Hayate Okuhara, Carla Raffaelli, Jari Nurmi
2020	J	`jnl`	Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors. CoRR Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed Elsayed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Joshua Alexander Harrison Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
2020	J	`jnl`	Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices. IEEE Des. Test Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón-Quirós, Davide Rossi, Andreas Burg, David Atienza
2020	J	`jnl`	Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elisabetta De Giovanni, Fabio Montagna, Benoît W. Denkinger, Simone Machetti, Miguel Peón-Quirós, Simone Benatti, Davide Rossi, Luca Benini, David Atienza
2020	—	`conf`	Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces. AICAS Pasquale Davide Schiavone, Davide Rossi, Yan Liu, Simone Benatti, Song Luan, Ian Williams, Luca Benini, Timothy G. Constandinou
2020	J	`jnl`	Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. CoRR Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2020	J	`jnl`	Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. Integr. Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2020	A	`conf`	TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi
2020	A	`conf`	XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. DATE Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini
2020	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. CoRR Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2019	—	`conf`	A PULP-based Parallel Power Controller for Future Exascale Systems. ICECS Andrea Bartolini, Davide Rossi, Antonio Mastrandrea, Christian Conficoni, Simone Benatti, Andrea Tilli, Luca Benini
2019	J	`jnl`	An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini
2019	—	`conf`	An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. NORCAS Hesam Zolfaghari, Davide Rossi, Jari Nurmi
2019	J	`jnl`	BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity. IEEE Trans. Biomed. Circuits Syst. Victor Javier Kartsch, Giuseppe Tagliavini, Marco Guermandi, Simone Benatti, Davide Rossi, Luca Benini
2019	Misc	`conf`	DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress. CODES+ISSS Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
2019	A	`conf`	Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA. DATE Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
2019	A	`conf`	Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters. DATE Florian Glaser, Germain Haugou, Davide Rossi, Qiuting Huang, Luca Benini
2019	J	`jnl`	Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine. IEEE J. Emerg. Sel. Topics Circuits Syst. Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
2019	J	`jnl`	Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
2019	J	`jnl`	Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing. IEEE Trans. Biomed. Circuits Syst. Simone Benatti, Fabio Montagna, Victor Javier Kartsch, Abbas Rahimi, Davide Rossi, Luca Benini
2019	—	`conf`	PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters. ICECS Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, Luca Benini
2019	J	`jnl`	PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors. CoRR Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, Luca Benini
2019	C	`conf`	Reducing Crossbar Costs in the Match-Action Pipeline. HPSR Hesam Zolfaghari, Davide Rossi, Jari Nurmi
2018	—	`conf`	A Fully Programmable eFPGA-Augmented SoC for Smart-Power Applications. ICECS Francesco Renzini, Davide Rossi, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo
2018	C	`conf`	A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. ISCAS Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi
2018	J	`jnl`	A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2018	C	`conf`	A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing. ISCAS Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
2018	J	`jnl`	A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems. Inf. Fusion Victor Javier Kartsch, Simone Benatti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
2018	A	`conf`	A transprecision floating-point platform for ultra-low power computing. DATE Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
2018	—	`conf`	Always-ON visual node with a hardware-software event-based binarized neural network inference engine. CF Manuele Rusci, Davide Rossi, Eric Flamand, Massimo Gottardi, Elisabetta Farella, Luca Benini
2018	—	`conf`	An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks. ASAP Hesam Zolfaghari, Davide Rossi, Jari Nurmi
2018	—	`conf`	Compressed Sensing Based Seizure Detection for an Ultra Low Power Multi-core Architecture. HPCS Roghayeh Aghazadeh, Fabio Montagna, Simone Benatti, Davide Rossi, Javad Frounchi
2018	A	`conf`	Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not? DATE Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza
2018	—	`conf`	GAP-8: A RISC-V SoC for AI at the Edge of the IoT. ASAP Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini
2018	—	`conf`	Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes. ISVLSI Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
2018	J	`jnl`	Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes. CoRR Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
2018	C	`conf`	Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. ISCAS Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2018	—	`conf`	Low-latency Packet Parsing in Software Defined Networks. NORCAS Hesam Zolfaghari, Davide Rossi, Jari Nurmi
2018	—	`conf`	Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. ESSCIRC Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini
2018	J	`jnl`	NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. ACM Trans. Reconfigurable Technol. Syst. Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2018	J	`jnl`	Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. IEEE Trans. Parallel Distributed Syst. Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2018	A*	`conf`	PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform. DAC Fabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, Luca Benini
2018	J	`jnl`	Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques. Microprocess. Microsystems Sajjad Nouri, Davide Rossi, Jari Nurmi
2018	C	`conf`	Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. ISCAS Martino Dazzi, Pierpaolo Palestri, Davide Rossi, Andrea Bandiziol, Igor Loi, David E. Bellasi, Luca Benini
2018	J	`jnl`	Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giuseppe Tagliavini, Davide Rossi, Andrea Marongiu, Luca Benini
2018	J	`jnl`	The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores. IEEE Trans. Multi Scale Comput. Syst. Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
2018	J	`jnl`	YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
2017	C	`conf`	A 142MOPS/mW integrated programmable array accelerator for smart visual processing. ISCAS Satyajit Das, Davide Rossi, Kevin J. M. Martin, Philippe Coussy, Luca Benini
2017	J	`jnl`	A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
2017	J	`jnl`	A Sub-mW IoT-Endnode for Always-On Visual Monitoring and Smart Triggering. IEEE Internet Things J. Manuele Rusci, Davide Rossi, Elisabetta Farella, Luca Benini
2017	J	`jnl`	A Transprecision Floating-Point Platform for Ultra-Low Power Computing. CoRR Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
2017	J	`jnl`	A sub-mW IoT-endnode for always-on visual monitoring and smart triggering. CoRR Manuele Rusci, Davide Rossi, Elisabetta Farella, Luca Benini
2017	—	`conf`	A wearable EEG-based drowsiness detection system with blink duration and alpha waves analysis. NER Victor Javier Kartsch, Simone Benatti, Davide Rossi, Luca Benini
2017	J	`jnl`	An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2017	—	`conf`	Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. ASP-DAC Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini
2017	J	`jnl`	Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017	J	`jnl`	Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. Microprocess. Microsystems Andres Gomez, Andrea Bartolini, Davide Rossi, Baris Can Kara, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
2017	J	`jnl`	Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. IEEE Trans. Very Large Scale Integr. Syst. Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini
2017	J	`jnl`	NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. CoRR Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2017	J	`jnl`	Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2017	J	`jnl`	Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. CoRR Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2017	—	`conf`	Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. PATMOS Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini
2017	—	`conf`	Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. PATMOS Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2017	—	`conf`	μDMA: An autonomous I/O subsystem for IoT end-nodes. PATMOS Antonio Pullini, Davide Rossi, Germain Haugou, Luca Benini
2016	—	`conf`	193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016	—	`conf`	A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD. ESSCIRC Marco Crescentini, Michele Biondi, Marco Bennati, P. Alberti, Giulia Luciani, Cinzia Tamburini, Matteo Pizzotti, Aldo Romani, Marco Tartagni, David E. Bellasi, Davide Rossi, Luca Benini, Marco Marchesi, Domenico Cristaudo, Roberto Canegallo
2016	C	`conf`	A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. ISCAS Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2016	J	`jnl`	A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2016	—	`conf`	Always-on motion detection with application-level error control on a near-threshold approximate computing platform. ICECS Giuseppe Tagliavini, Andrea Marongiu, Davide Rossi, Luca Benini
2016	J	`jnl`	An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2016	—	`conf`	Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube. ARCS Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2016	A	`conf`	Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms. DATE Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi, Luca Benini
2016	—	`conf`	Energy-efficient design of an always-on smart visual trigger. ISC2 Manuele Rusci, Davide Rossi, Michela Lecca, Massimo Gottardi, Luca Benini, Elisabetta Farella
2016	J	`jnl`	PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. J. Signal Process. Syst. Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2016	J	`jnl`	Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
2016	—	`conf`	Scalable EEG seizure detection on an ultra low power multi-core architecture. BioCAS Simone Benatti, Fabio Montagna, Davide Rossi, Luca Benini
2016	A	`conf`	Towards near-threshold server processors. DATE Ali Pahlevan, Javier Picorel, Arash Pourhabibi Zarandi, Davide Rossi, Marina Zapater, Andrea Bartolini, Pablo García Del Valle, David Atienza, Luca Benini, Babak Falsafi
2016	—	`conf`	YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. ISVLSI Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
2016	J	`jnl`	YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. CoRR Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
2015	J	`jnl`	A Modular Shared L2 Memory Design for 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2015	—	`conf`	Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC Adam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg
2015	—	`conf`	Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters. Conf. Computing Frontiers Igor Loi, Davide Rossi, Germain Haugou, Michael Gautschi, Luca Benini
2015	A	`conf`	High performance AXI-4.0 based interconnect for extensible smart memory cubes. DATE Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2015	—	`conf`	PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
2015	A	`conf`	Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. DATE Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez
2015	—	`conf`	Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. ISVLSI Giuseppe Tagliavini, Davide Rossi, Luca Benini, Andrea Marongiu
2014	—	`conf`	Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory. ACM Great Lakes Symposium on VLSI Michael Gautschi, Davide Rossi, Luca Benini
2014	—	`conf`	Energy-efficient vision on the PULP platform for ultra-low power parallel computing. SiPS Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2014	A	`conf`	Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors. DATE Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Benini
2014	J	`jnl`	Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Davide Rossi, Claudio Mucci, Matteo Pizzotti, Luca Perugini, Roberto Canegallo, Roberto Guerrieri
2014	—	`conf`	Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters. Conf. Computing Frontiers Davide Rossi, Igor Loi, Germain Haugou, Luca Benini
2013	—	`conf`	A variation tolerant architecture for ultra low power multi-processor cluster. PATMOS Daniele Bortolotti, Davide Rossi, Andrea Bartolini, Luca Benini
2013	J	`jnl`	Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor. IEEE Trans. Very Large Scale Integr. Syst. Davide Rossi, Claudio Mucci, Fabio Campi, Simone Spolzino, Luca Vanzolini, Henning Sahlbach, Sean Whitty, Rolf Ernst, Wolfram Putzke-Röming, Roberto Guerrieri
2013	—	`conf`	Exploiting body biasing for leakage reduction: A case study. ISVLSI Andrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini
2011	J	`jnl`	The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform. Int. J. Parallel Program. Arnaud Grasset, Philippe Millet, Philippe Bonnot, Sami Yehia, Wolfram Putzke-Röming, Fabio Campi, Alberto Rosti, Michael Hübner, Nikolaos S. Voros, Davide Rossi, Henning Sahlbach, Rolf Ernst
2010	J	`jnl`	A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing. IEEE J. Solid State Circuits Davide Rossi, Fabio Campi, Simone Spolzino, Stefano Pucillo, Roberto Guerrieri
2010	J	`jnl`	A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations. J. Syst. Archit. Claudio Brunelli, Fabio Garzia, Davide Rossi, Jari Nurmi
2009	—	`conf`	A heterogeneous digital signal processor implementation for dynamically reconfigurable computing. CICC Davide Rossi, Fabio Campi, Antonio Deledda, Simone Spolzino, Stefano Pucillo
2009	—	`conf`	A multi-core signal processor for heterogeneous reconfigurable computing. SoC Davide Rossi, Fabio Campi, Antonio Deledda, Claudio Mucci, Stefano Pucillo, Sean Whitty, Rolf Ernst, Stéphane Chevobbe, Stéphane Guyetant, Matthias Kühnle, Michael Hübner, Jürgen Becker, Wolfram Putzke-Röming
2009	—	`conf`	RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip. SoC Fabio Campi, Ralf König, Michael Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, Antonio Deledda, Davide Rossi, Alberto Pasini, Michael Hübner, Jürgen Becker, Roberto Guerrieri
2008	J	`jnl`	Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications. J. Syst. Archit. Claudio Brunelli, Fabio Campi, Claudio Mucci, Davide Rossi, Tapani Ahonen, Juha Kylliäinen, Fabio Garzia, Jari Nurmi
2008	A	`conf`	Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture. IPDPS Fabio Garzia, Claudio Brunelli, Davide Rossi, Jari Nurmi
2005	—	`conf`	A FPGA Implementation of An Open-Source Floating-Point Computation System. SoC Claudio Brunelli, Fabio Garzia, Jari Nurmi, Claudio Mucci, Fabio Campi, Davide Rossi