Davide Pandini

41 papers A* 2A 4C 5Journal 7Unranked 23

Year	Rank	Type	Title / Venue / Authors
2013	—	`conf`	Design methodology for low-power embedded microprocessors. PATMOS Andrea Manuzzato, Fabio Campi, Valentino Liberali, Davide Pandini
2013	—	`conf`	Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers. EMC Compo Marco Cazzaniga, Patrice Joubert Doriol, Aurora Sanna, Emmanuel Blanc, Valentino Liberali, Davide Pandini
2013	—	`conf`	Evaluating the impact of substrate on power integrity in industrial microcontrollers. PATMOS Marco Cazzaniga, Patrice Joubert Doriol, Emmanuel Blanc, Valentino Liberali, Davide Pandini
2013	—	`conf`	Exploiting body biasing for leakage reduction: A case study. ISVLSI Andrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini
2011	—	`conf`	A design methodology for the automatic sizing of standard-cell libraries. ACM Great Lakes Symposium on VLSI Christian Pilato, Fabrizio Ferrandi, Davide Pandini
2011	—	`conf`	Evaluating Static CMOS Complex Cells in Technology Mapping. ARCS Workshops Christian Pilato, Fabrizio Ferrandi, Davide Pandini
2011	—	`conf`	SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini
2010	—	`conf`	A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells. ISVLSI Christian Pilato, Fabrizio Ferrandi, Davide Pandini
2010	J	`jnl`	Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization. J. Low Power Electron. Nikolaos Andrikos, Luciano Lavagno, Fabio Campi, Davide Pandini
2009	J	`jnl`	Clock-tree synthesis for low-EMI design. J. Embed. Comput. Davide Pandini, Guido A. Repetto, Vincenzo Sinisi
2009	A	`conf`	EMC-aware design on a microcontroller for automotive applications. DATE Patrice Joubert Doriol, Yamarita Villavicencio, Cristiano Forzan, Mario Rotigni, Giovanni Graziosi, Davide Pandini
2009	J	`jnl`	Statistical static timing analysis: A survey. Integr. Cristiano Forzan, Davide Pandini
2009	—	`conf`	Variability in Advanced Nanometer Technologies: Challenges and Solutions. PATMOS Davide Pandini
2008	A	`conf`	Robust Design-for-Productization Practices for High Quality Automotive Products. ITC Paolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello
2007	A*	`conf`	A Fully-Automated Desynchronization Flow for Synchronous Circuits. DAC Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou
2007	—	`conf`	A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. ISVLSI Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto
2007	—	`conf`	Clock Distribution Techniques for Low-EMI Design. PATMOS Davide Pandini, Guido A. Repetto, Vincenzo Sinisi
2007	C	`conf`	Computing and design for software and silicon manufacturing. VLSI-SoC Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi
2007	C	`conf`	Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. IOLTS Davide Pandini
2007	J	`jnl`	Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis CoRR Cristiano Forzan, Davide Pandini
2007	—	`conf`	Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. PATMOS Davide Pandini
2007	C	`conf`	Why we need statistical static timing analysis. ICCD Cristiano Forzan, Davide Pandini
2006	—	`conf`	An ultra-low energy asynchronous processor for Wireless Sensor Networks. ASYNC Luca Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago
2006	J	`jnl`	Power Supply Selective Mapping for Accurate Timing Analysis. J. Low Power Electron. Cristiano Forzan, Davide Pandini, Mariagrazia Graziano
2006	—	`conf`	Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design. PATMOS Davide Pandini, Guido A. Repetto
2005	—	`conf`	A complete methodology for an accurate static noise analysis. ACM Great Lakes Symposium on VLSI Cristiano Forzan, Davide Pandini
2005	—	`conf`	Including Power Supply Variations into Static Timing Analysis: Methodology and Flow. SoCC Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
2005	A	`conf`	Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis. DATE Cristiano Forzan, Davide Pandini
2005	—	`conf`	Power Supply Selective Mapping for Accurate Timing Analysis. PATMOS Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
2004	—	`conf`	A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ACM Great Lakes Symposium on VLSI Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini
2004	C	`conf`	Design Methodologies and Architecture Solutions for High-Performance Interconnects. ICCD Davide Pandini, Cristiano Forzan, Livio Baldi
2003	—	`conf`	Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2003	J	`jnl`	Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002	A	`conf`	Congestion-Aware Logic Synthesis. DATE Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002	—	`conf`	Understanding and addressing the impact of wiring congestion during technology mapping. ISPD Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2000	—	`conf`	Crosstalk Aware Static Timing Analysis: A Two Step Approach. ISQED Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro
1998	—	`conf`	Nonlinear macromodels of large coupled interconnect networks. CICC Bruno Franzini, Cristiano Forzan, Davide Pandini, Y. Liu, Carlo Guardiani
1998	—	`conf`	Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. ASP-DAC Davide Pandini, Primo Scandolara, Carlo Guardiani
1995	J	`jnl`	Optimum CMOS stack generation with analog constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Enrico Malavasi, Davide Pandini
1994	A*	`conf`	Simultaneous Placement and Module Optimization of Analog IC's. DAC Edoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli
1993	C	`conf`	Automatic Generation of Transistor Stacks for CMOS Analog Layout. ISCAS Valentino Liberali, Enrico Malavasi, Davide Pandini