Davide De Caro

98 papers A 1C 10Journal 60Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Analytical Error Evaluation and Hardware Implementation of Approximate Negation Circuits. IEEE Access Ettore Napoli, Efstratios Zacharelos, Davide De Caro, Gennaro Di Meo, Antonio G. M. Strollo
2025	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. ACM Comput. Surv. Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke, Stefania Perri
2025	C	`conf`	A novel approximate multiplier based on improved logarithmic and antilogarithmic conversions. ISCAS Gennaro Di Meo, Davide De Caro, Luca Tegazzini, Ettore Napoli, Antonio G. M. Strollo
2025	—	`conf`	Design of Hardware-Efficient Radix-2 PRIME Camillo Perna, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo
2025	—	`conf`	Design of a Hardware-Efficient Accumulator for Applications with Large Guard Bit Requirements. ICECS Luca Tegazzini, Gennaro Di Meo, Nicola Petra, Davide De Caro, Antonio G. M. Strollo
2025	J	`jnl`	High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm. IEEE Trans. Circuits Syst. II Express Briefs Luca Tegazzini, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo
2025	J	`jnl`	Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. Gennaro Di Meo, Antonio Giuseppe Maria Strollo, Davide De Caro, Luca Tegazzini, Ettore Napoli
2025	J	`jnl`	Novel Approximate Floating-Point Adder With Runtime Tunable Precision. IEEE Access Luca Tegazzini, Gennaro Di Meo, Aldo Torino, Francesco Del Prete, Davide De Caro, Claudio Parrella, Antonio Giuseppe Maria Strollo
2024	J	`jnl`	Approximate MAC Unit Using Static Segmentation. IEEE Trans. Emerg. Top. Comput. Gennaro Di Meo, Gerardo Saggese, Antonio G. M. Strollo, Davide De Caro
2024	—	`conf`	Design of a Hardware-Efficient Floating-Point Multiplier with Dynamic Segmentation. PRIME Luca Tegazzini, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo
2023	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
2023	J	`jnl`	A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
2023	J	`jnl`	Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error. IEEE Trans. Circuits Syst. I Regul. Pap. Gennaro Di Meo, Antonio Giuseppe Maria Strollo, Davide De Caro
2022	J	`jnl`	A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error. IEEE Trans. Circuits Syst. I Regul. Pap. Gennaro Di Meo, Davide De Caro, Giacinto Paolo Saggese, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
2022	—	`conf`	A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section. PRIME Gennaro Di Meo, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2022	J	`jnl`	Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements. IEEE Trans. Circuits Syst. I Regul. Pap. Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra, Giacinto Paolo Saggese, Gennaro Di Meo
2020	J	`jnl`	A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications. IEEE Trans. Circuits Syst. Davide De Caro, Gennaro Di Meo, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
2020	C	`conf`	A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. ISCAS Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2020	J	`jnl`	A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. IEEE Trans. Circuits Syst. I Regul. Pap. Ettore Napoli, Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo
2020	J	`jnl`	Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra, Gennaro Di Meo
2020	C	`conf`	Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor. ISCAS Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra, Gennaro Di Meo
2020	—	`conf`	Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding. ICECS Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2019	J	`jnl`	An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. Circuits Syst. Signal Process. Gerardo Castellano, Davide De Caro, Darjn Esposito, Paolo Bifulco, Ettore Napoli, Nicola Petra, Emilio Andreozzi, Mario Cesarelli, Antonio G. M. Strollo
2019	J	`jnl`	Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. Circuits Syst. Signal Process. Darjn Esposito, Davide De Caro, Gennaro Di Meo, Ettore Napoli, Antonio G. M. Strollo
2019	—	`conf`	Variable-Rounded LMS Filter for Low-Power Applications. ApplePies Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2018	J	`jnl`	A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability. IEEE Trans. Circuits Syst. I Regul. Pap. Michele De Martino, Davide De Caro, Darjn Esposito, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
2018	J	`jnl`	An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands. IEEE J. Solid State Circuits Daniele Montanari, Gerardo Castellano, Ehsan Kargaran, Giacomo Pini, Saheed Tijani, Davide De Caro, Antonio Giuseppe Maria Strollo, Danilo Manstretta, Rinaldo Castello
2018	J	`jnl`	Approximate Multipliers Based on New Approximate Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. Darjn Esposito, Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra
2018	—	`conf`	Design of Low-Power Approximate LMS Filters with Precision-Scalability. ApplePies Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
2018	C	`conf`	On the Use of Approximate Multipliers in LMS Adaptive Filters. ISCAS Darjn Esposito, Gennaro Di Meo, Davide De Caro, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo
2018	—	`conf`	Quality-Scalable Approximate LMS Filter. ICECS Darjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
2018	—	`conf`	Stall-Aware Fixed-Point Implementation of LMS Filters. PRIME Darjn Esposito, Gennaro Di Meo, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2017	J	`jnl`	A SISO Register Circuit Tailored for Input Data with Low Transition Probability. IEEE Trans. Computers Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio G. M. Strollo
2017	J	`jnl`	An Efficient Digital Background Control for Hybrid Transformer-Based Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. Gerardo Castellano, Daniele Montanari, Davide De Caro, Danilo Manstretta, Antonio Giuseppe Maria Strollo
2017	J	`jnl`	Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Ettore Napoli, Darjn Esposito, Gerardo Castellano, Nicola Petra, Antonio G. M. Strollo
2017	C	`conf`	On the use of approximate adders in carry-save multiplier-accumulators. ISCAS Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2017	J	`jnl`	Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise. IEEE Trans. Circuits Syst. I Regul. Pap. Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio Giuseppe Maria Strollo
2017	J	`jnl`	Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines. Circuits Syst. Signal Process. Davide De Caro, Fabio Tessitore, Gianfranco Vai, Gerardo Castellano, Ettore Napoli, Nicola Petra, Claudio Parrella, Antonio G. M. Strollo
2016	—	`conf`	A low power control system for real-time tuning of a hybrid transformer-based receiver. ICECS Gerardo Castellano, Davide De Caro, Antonio G. M. Strollo, Danilo Manstretta
2016	C	`conf`	Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. ISCAS Darjn Esposito, Gerardo Castellano, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2016	J	`jnl`	Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. IEEE Trans. Circuits Syst. I Regul. Pap. Darjn Esposito, Davide De Caro, Antonio Giuseppe Maria Strollo
2015	J	`jnl`	A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. IEEE J. Solid State Circuits Davide De Caro, Fabio Tessitore, Gianfranco Vai, Nicola Imperato, Nicola Petra, Ettore Napoli, Claudio Parrella, Antonio G. M. Strollo
2015	J	`jnl`	Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. Integr. Mariangela Genovese, Paolo Bifulco, Davide De Caro, Ettore Napoli, Nicola Petra, Maria Romano, Mario Cesarelli, Antonio G. M. Strollo
2015	J	`jnl`	Variable Latency Speculative Han-Carlson Adder. IEEE Trans. Circuits Syst. I Regul. Pap. Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo
2014	J	`jnl`	Accurate Fixed-Point Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs Davide De Caro, Mariangela Genovese, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2014	J	`jnl`	Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. Integr. Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2014	—	`conf`	Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint. ApplePies Davide De Caro, Michele De Martino, Nicola Petra, Antonio G. M. Strollo
2014	J	`jnl`	High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. IEEE Trans. Circuits Syst. I Regul. Pap. Alessandro Cilardo, Davide De Caro, Nicola Petra, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo
2014	J	`jnl`	Truncated squarer with minimum mean-square error. Microelectron. J. Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
2013	J	`jnl`	FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video. J. Electr. Comput. Eng. Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2013	J	`jnl`	Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo, Fabio Tessitore, Ettore Napoli
2013	J	`jnl`	Glitch-Free NAND-Based Digitally Controlled Delay-Lines. IEEE Trans. Very Large Scale Integr. Syst. Davide De Caro
2013	J	`jnl`	NORA based TDC in 90 nm CMOS. Microelectron. J. Nicola Petra, Sebastiano Russo, Davide De Caro, Ettore Napoli, Giancarlo Barbarino, Antonio G. M. Strollo
2012	J	`jnl`	A high-speed differential resistor ladder. Microelectron. J. Davide De Caro, Marino Coppola, Nicola Petra
2012	J	`jnl`	An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines. IEEE Trans. Very Large Scale Integr. Syst. Maurizio Costagliola, Davide De Caro, Antonio Girardi, Roberto Izzi, Niccolò Rinaldi, Marco Spirito, Paolo Spirito
2012	J	`jnl`	Efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies. Int. J. Circuit Theory Appl. Tommaso Addabbo, Davide De Caro, Ada Fort, Nicola Petra, Santina Rocchi, Valerio Vignoli
2011	J	`jnl`	Design of Fixed-Width Multipliers With Linear Compensation Function. IEEE Trans. Circuits Syst. I Regul. Pap. Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
2011	J	`jnl`	Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2011	J	`jnl`	Efficient Logarithmic Converters for Digital Signal Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2011	J	`jnl`	Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations. IEEE Trans. Computers Antonio G. M. Strollo, Davide De Caro, Nicola Petra
2010	J	`jnl`	A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. IEEE J. Solid State Circuits Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio G. M. Strollo, Claudio Parrella
2010	C	`conf`	A novel truncated squarer with linear compensation function. ISCAS Valeria Garofalo, Marino Coppola, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2010	C	`conf`	Fixed-width CSD multipliers with minimum mean square error. ISCAS Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Valeria Garofalo, Ettore Napoli, Marino Coppola, Pietro Todisco
2010	C	`conf`	High-speed differential resistor ladder for A/D converters. ISCAS Davide De Caro, Marino Coppola, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo, Valeria Garofalo
2010	J	`jnl`	Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. IEEE Trans. Circuits Syst. I Regul. Pap. Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
2009	J	`jnl`	Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2009	J	`jnl`	High-Performance Special Function Unit for Programmable 3-D Graphics Processors. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2008	J	`jnl`	A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS. IEEE J. Solid State Circuits Andrea Bonfanti, Davide De Caro, Alfio Dario Grasso, Salvatore Pennisi, Carlo Samori, Antonio G. M. Strollo
2008	J	`jnl`	A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 µm CMOS. IEEE J. Solid State Circuits Antonio Giuseppe Maria Strollo, Davide De Caro, Nicola Petra
2008	C	`conf`	A high performance floating-point special function unit using constrained piecewise quadratic approximation. ISCAS Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2008	—	`conf`	Constrained piecewise polinomial approximation for hardware implementation of elementary functions. ICECS Antonio G. M. Strollo, Davide De Caro, Nicola Petra, Ettore Napoli, Valeria Garofalo
2008	—	`conf`	Low error truncated multipliers for DSP applications. ICECS Valeria Garofalo, Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli
2008	J	`jnl`	Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2007	J	`jnl`	A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS. IEEE J. Solid State Circuits Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo
2007	J	`jnl`	A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique. IEEE J. Solid State Circuits Antonio Giuseppe Maria Strollo, Davide De Caro, Nicola Petra
2007	J	`jnl`	A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme. IEEE Trans. Computers Nicola Petra, Davide De Caro, Antonio G. M. Strollo
2007	—	`conf`	Design of fixed-width multipliers with minimum mean square error. ECCTD Nicola Petra, Davide De Caro, Antonio G. M. Strollo
2007	—	`conf`	High Speed Galois Fields GF(2 ECCTD Nicola Petra, Davide De Caro, Antonio G. M. Strollo
2006	—	`conf`	A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS. ISSCC Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2006	—	`conf`	A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS. ISSCC Davide De Caro, Nicola Petra, Antonio G. M. Strollo
2005	—	`conf`	A high-speed sense-amplifier based flip-flop. ECCTD Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo
2005	J	`jnl`	A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. Very Large Scale Integr. Syst. Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
2005	J	`jnl`	Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers. IEEE Trans. Circuits Syst. II Express Briefs Antonio G. M. Strollo, Nicola Petra, Davide De Caro
2005	J	`jnl`	High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation. IEEE J. Solid State Circuits Davide De Caro, Antonio Giuseppe Maria Strollo
2005	J	`jnl`	High-performance direct digital frequency synthesizers using piecewise-polynomial approximation. IEEE Trans. Circuits Syst. I Regul. Pap. Davide De Caro, Antonio G. M. Strollo
2004	—	`conf`	An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS. ESSCIRC Antonio Giuseppe Maria Strollo, Nicola Petra, Davide De Caro, Ettore Napoli
2004	J	`jnl`	Direct digital frequency synthesizers with polynomial hyperfolding technique. IEEE Trans. Circuits Syst. II Express Briefs Davide De Caro, Ettore Napoli, Antonio G. M. Strollo
2004	—	`conf`	High-speed direct digital frequency synthesizers in 0.25-μm CMOS. CICC Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
2003	J	`jnl`	Booth folding encoding for high performance squarer circuits. IEEE Trans. Circuits Syst. II Express Briefs Antonio G. M. Strollo, Davide De Caro
2003	—	`conf`	Direct digital frequency synthesis with dual-slope approach. ESSCIRC Antonio Giuseppe Maria Strollo, Davide De Caro, Ettore Napoli, Nicola Petra
2003	J	`jnl`	Direct digital frequency synthesizers exploiting piecewise linear Chebyshev approximation. Microelectron. J. Antonio G. M. Strollo, Davide De Caro
2002	—	`—`	Architetture innovative per la sintesi digitale diretta di frequenza. Davide De Caro
2002	—	`conf`	ROM-less direct digital frequency synthesizers exploiting polynomial approximation. ICECS Davide De Caro, Ettore Napoli, Antonio G. M. Strollo
2002	—	`conf`	Shuffled serial adder: an area-latency effective serial adder. ICECS Giacinto Paolo Saggese, Antonio G. M. Strollo, Nicola Mazzocca, Davide De Caro
2001	—	`conf`	A reconfigurable 2D convolver for real-time SAR imaging. ICECS Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese
2001	—	`conf`	New design of squarer circuits using Booth encoding and folding techniques. ICECS Antonio G. M. Strollo, Ettore Napoli, Davide De Caro
2001	—	`conf`	Test pattern generator for hybrid testing of combinational circuits. ICECS Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo
2000	A	`conf`	New clock-gating techniques for low-power flip-flops. ISLPED Antonio G. M. Strollo, Ettore Napoli, Davide De Caro