David Z. Pan - RankMe

499 papers A* 69A 85B 5C 5Misc 5Journal 195Unranked 128

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AI+HW 2035: Shaping the Next Decade. CoRR Deming Chen, Jason Cong, Azalia Mirhoseini, Christos Kozyrakis, Subhasish Mitra, Jinjun Xiong, Cliff Young, Anima Anandkumar, Michael L. Littman, Aron Kirschen, Sophia Shao, Serge Leef, Naresh R. Shanbhag, Dejan S. Milojicic, Michael Schulte, Gert Cauwenberghs, Jerry M. Chow, Tri Dao, Kailash Gopalakrishnan, Richard Ho, Hoshik Kim, Kunle Olukotun, David Z. Pan, Mark Ren, Dan Roth, Aarti Singh, Yizhou Sun, Yusu Wang, Yann LeCun, Ruchir Puri
2026	—	`conf`	ENLighten: Lighten the Transformer, Enable Efficient Optical Acceleration. ASP-DAC Hanqing Zhu, Zhican Zhou, Shupeng Ning, Xuhao Wu, Ray T. Chen, Yating Wan, David Z. Pan
2026	J	`jnl`	GLANCE: Gaze-Led Attention Network for Compressed Edge-inference. CoRR Neeraj Solanki, Hong Ding, Sepehr Tabrizchi, Ali Shafiee Sarvestani, Shaahin Angizi, David Z. Pan, Arman Roohi
2026	—	`conf`	GrandPlan: Differentiable, Simultaneous Top-Level Floorplanning and Partition-Level Cell Placement for Large-Scale IP-Cores. ISPD Zhili Xiong, Yi-Chen Lu, David Z. Pan, Haoxing Ren
2026	J	`jnl`	Report for NSF Workshop on AI for Electronic Design Automation. CoRR Deming Chen, Vijay Ganesh, Weikai Li, Yingyan Celine Lin, Yong Liu, Subhasish Mitra, David Z. Pan, Ruchir Puri, Jason Cong, Yizhou Sun
2026	—	`conf`	TransOpt: A Scalable Transistor-Level Placement and Routing Optimization Framework Beyond Standard Cells. ISPD Chen-Hao Hsu, David Z. Pan
2025	J	`jnl`	A Hardware-Efficient Photonic Tensor Core: Accelerating Deep Neural Networks with Structured Compression. CoRR Shupeng Ning, Hanqing Zhu, Chenghao Feng, Jiaqi Gu, David Z. Pan, Ray T. Chen
2025	—	`conf`	APOLLO: SGD-like Memory, AdamW-level Performance. MLSys Hanqing Zhu, Zhenyu Zhang, Wenyan Cong, Xi Liu, Sem Park, Vikas Chandra, Bo Long, David Z. Pan, Zhangyang Wang, Jinwon Lee
2025	J	`jnl`	AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs. CoRR Yao Lai, Souradip Poddar, Sungyoung Lee, Guojin Chen, Mengkang Hu, Bei Yu, Ping Luo, David Z. Pan
2025	A*	`conf`	AnalogCoder: Analog Circuit Design via Training-Free Code Generation. AAAI Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, Ping Luo
2025	J	`jnl`	Can Test-Time Scaling Improve World Foundation Model? CoRR Wenyan Cong, Hanqing Zhu, Peihao Wang, Bangya Liu, Dejia Xu, Kevin Wang, David Z. Pan, Yan Wang, Zhiwen Fan, Zhangyang Wang
2025	Misc	`conf`	ChipMnd: LLMs for Agile Chip Design. VTS Farshad Firouzi, David Z. Pan, Jiaqi Gu, Bahar J. Farahani, Jayeeta Chaudhuri, Ziang Yin, Pingchuan Ma, Peter Domanski, Krishnendu Chakrabarty
2025	A	`conf`	Differentiable Timing-Driven FPGA Placement with Smooth Optimization and ML-Based Delay Calibration. ICCAD Yu-Kang Lin, Zhili Xiong, David Z. Pan
2025	J	`jnl`	ENLighten: Lighten the Transformer, Enable Efficient Optical Acceleration. CoRR Hanqing Zhu, Zhican Zhou, Shupeng Ning, Xuhao Wu, Ray T. Chen, Yating Wan, David Z. Pan
2025	J	`jnl`	Fine-Tuning Masked Diffusion for Provable Self-Correction. CoRR Jaeyeon Kim, Seunggeun Kim, Taekyun Lee, David Z. Pan, Hyeji Kim, Sham M. Kakade, Sitan Chen
2025	J	`jnl`	From Classical Algorithms to AI: Evolving Trends in VLSI Physical Design Automation. IEEE Des. Test David Z. Pan, Yao-Wen Chang, Chen-Hao Hsu, Yang Hsu
2025	A	`conf`	GPU Acceleration for Versatile Buffer Insertion. ICCAD Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu
2025	J	`jnl`	HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization. CoRR Souradip Poddar, Chia-Tung Ho, Ziming Wei, Weidong Cao, Haoxing Ren, David Z. Pan
2025	J	`jnl`	ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar
2025	A*	`conf`	INSIGHT: A Universal Neural Simulator Framework for Analog Circuits with Autoregressive Transformers. DAC Souradip Poddar, Youngmin Oh, Yao Lai, Hanqing Zhu, Bosun Hwang, David Z. Pan
2025	A	`conf`	Invited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to Layout. ICCAD Hyunsu Chae, Seunggeun Kim, Souradip Poddar, Xiaohan Gao, Sensen Li, David Z. Pan
2025	—	`conf`	Invited: Shaping the Future of Interconnected Physical Design. ISPD David Z. Pan
2025	A*	`conf`	Late Breaking Results: Breaking Symmetry - Unconventional Placement of Analog Circuits using Multi-Level Multi-Agent Reinforcement Learning. DAC Supriyo Maji, Linran Zhao, Souradip Poddar, David Z. Pan
2025	J	`jnl`	Late Breaking Results: Breaking Symmetry- Unconventional Placement of Analog Circuits using Multi-Level Multi-Agent Reinforcement Learning. CoRR Supriyo Maji, Linran Zhao, Souradip Poddar, David Z. Pan
2025	A	`conf`	M3: Mamba-assisted Multi-Circuit Optimization via Model-based RL with Effective Scheduling. ICCAD Youngmin Oh, Jinje Park, Taejin Paik, Seunggeun Kim, Suwan Kim, Yoon Hyeok Lee, David Z. Pan
2025	—	`conf`	ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA. ASP-DAC Hyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan
2025	A	`conf`	MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation. ICCAD Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, Bei Yu
2025	J	`jnl`	Multiobjective Optimization for Common-Centroid Placement of Analog Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Supriyo Maji, Hyungjoo Park, Gi moon Hong, Souradip Poddar, David Z. Pan
2025	A	`conf`	NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times. ICCAD Ziyi Wang, Fangzhou Liu, Tsung-Yi Ho, David Z. Pan, Bei Yu
2025	J	`jnl`	PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors. IEEE Comput. Archit. Lett. Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, Shaahin Angizi, Arman Roohi
2025	A	`conf`	PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning. ICCAD Seunggeun Kim, Ziyi Wang, Sungyoung Lee, Youngmin Oh, Hanqing Zhu, Doyun Kim, David Z. Pan
2025	J	`jnl`	Physical Design for Heterogeneous Integration: Challenges and Opportunities. IEEE Des. Test Yao-Wen Chang, David Z. Pan
2025	J	`jnl`	Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits. CoRR Sungyoung Lee, Ziyi Wang, Seunggeun Kim, Taekyun Lee, David Z. Pan
2025	J	`jnl`	The Path Not Taken: RLVR Provably Learns Off the Principals. CoRR Hanqing Zhu, Zhenyu Zhang, Hanxian Huang, DiJia Su, Zechun Liu, Jiawei Zhao, Igor Fedorov, Hamed Pirsiavash, Zhizhou Sha, Jinwon Lee, David Z. Pan, Zhangyang Wang, Yuandong Tian, Kai Sheng Tai
2025	J	`jnl`	TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits. CoRR Ziming Wei, Zichen Kong, Yuan Wang, David Z. Pan, Xiyuan Tang
2025	A*	`conf`	TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology. DAC Chen-Hao Hsu, David Z. Pan, Laurent Perron, Frédéric Didier, Xiaoqing Xu, Hao Chen
2025	J	`jnl`	UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings. CoRR Jiajun Qin, Yuan Pu, Zhuolun He, Seunggeun Kim, David Z. Pan, Bei Yu
2024	A	`conf`	A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. DATE Souradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, David Z. Pan
2024	Misc	`conf`	A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs. FCCM Zhili Xiong, Rachel Selina Rajarathnam, David Z. Pan
2024	J	`jnl`	APOLLO: SGD-like Memory, AdamW-level Performance. CoRR Hanqing Zhu, Zhenyu Zhang, Wenyan Cong, Xi Liu, Sem Park, Vikas Chandra, Bo Long, David Z. Pan, Zhangyang Wang, Jinwon Lee
2024	A	`conf`	Analog Transistor Placement Optimization Considering Nonlinear Spatial Variations. DATE Supriyo Maji, Sungyoung Lee, David Z. Pan
2024	J	`jnl`	AnalogCoder: Analog Circuit Design via Training-Free Code Generation. CoRR Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, Ping Luo
2024	A*	`conf`	Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays. ISCA Hanrui Wang, Pengyu Liu, Daniel Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han
2024	—	`conf`	Automated Physical Design Watermarking Leveraging Graph Neural Networks. MLCAD Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar
2024	J	`jnl`	Automated Physical Design Watermarking Leveraging Graph Neural Networks. CoRR Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar
2024	B	`conf`	Better Together: Combining Analytical and Annealing Methods for FPGA Placement. FPL Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan
2024	A	`conf`	Differentiable Edge-based OPC. ICCAD Guojin Chen, Haoyu Yang, Haoxing Mark Ren, Bei Yu, David Z. Pan
2024	J	`jnl`	Differentiable Edge-based OPC. CoRR Guojin Chen, Haoyu Yang, Haoxing Ren, Bei Yu, David Z. Pan
2024	J	`jnl`	ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection. CoRR Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar
2024	J	`jnl`	INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformers. CoRR Souradip Poddar, Youngmin Oh, Yao Lai, Hanqing Zhu, Bosun Hwang, David Z. Pan
2024	J	`jnl`	ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2024	B	`conf`	ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. ASPDAC Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan
2024	J	`jnl`	LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. CoRR Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan
2024	A*	`conf`	Lightening-Transformer: A Dynamically-Operated Optically-Interconnected Photonic Transformer Accelerator. HPCA Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Zixuan Jiang, Zhekai Zhang, Rongxing Tang, Chenghao Feng, Song Han, Ray T. Chen, David Z. Pan
2024	J	`jnl`	M3: Mamba-assisted Multi-Circuit Optimization via MBRL with Effective Scheduling. CoRR Youngmin Oh, Jinje Park, Seunggeun Kim, Taejin Paik, David Z. Pan, Bosun Hwang
2024	J	`jnl`	Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors. CoRR Supriyo Maji, Hyungjoo Park, Gi moon Hong, Souradip Poddar, David Z. Pan
2024	J	`jnl`	Open-Source Differentiable Lithography Imaging Framework. CoRR Guojin Chen, Hao Geng, Bei Yu, David Z. Pan
2024	A*	`conf`	PACE: Pacing Operator Learning to Accurate Optical Field Simulation for Complicated Photonic Devices. NeurIPS Hanqing Zhu, Wenyan Cong, Guojin Chen, Shupeng Ning, Ray T. Chen, Jiaqi Gu, David Z. Pan
2024	J	`jnl`	PACE: Pacing Operator Learning to Accurate Optical Field Simulation for Complicated Photonic Devices. CoRR Hanqing Zhu, Wenyan Cong, Guojin Chen, Shupeng Ning, Ray T. Chen, Jiaqi Gu, David Z. Pan
2024	J	`jnl`	Photonic-Electronic Integrated Circuits for High-Performance Computing and AI Accelerator. CoRR Shupeng Ning, Hanqing Zhu, Chenghao Feng, Jiaqi Gu, Zhixing Jiang, Zhoufeng Ying, Jason Midkiff, Sourabh Jain, May H. Hlaing, David Z. Pan, Ray T. Chen
2024	J	`jnl`	PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arman Roohi, Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, Shaahin Angizi
2024	J	`jnl`	Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang
2024	A	`conf`	PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design. ICCAD Hyunsu Chae, Hao Yu, Sensen Li, David Z. Pan
2024	J	`jnl`	QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits. CoRR Tianlong Chen, Zhenyu Zhang, Hanrui Wang, Jiaqi Gu, Zirui Li, David Z. Pan, Frederic T. Chong, Song Han, Zhangyang Wang
2024	—	`conf`	SRC: Sustainable Reactive Computing for Battery-free Edge Intelligence. IGSC Sepehr Tabrizchi, Nedasadat Taheri, Justin Feng, Nader Sehatbakhsh, David Z. Pan, Arman Roohi
2024	A*	`conf`	Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs. NeurIPS Yao Lai, Jinxin Liu, David Z. Pan, Ping Luo
2024	J	`jnl`	Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs. CoRR Yao Lai, Jinxin Liu, David Z. Pan, Ping Luo
2024	A	`conf`	Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS. DATE Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu
2024	J	`jnl`	Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS. CoRR Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu
2024	B	`conf`	Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches (Invited Paper). ASPDAC Supriyo Maji, Ahmet Faruk Budak, Souradip Poddar, David Z. Pan
2024	B	`conf`	TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design. ASPDAC Chen-Hao Hsu, Xiaoqing Xu, Hao Chen, Dino Ruic, David Z. Pan
2024	J	`jnl`	Ultrafast Source Mask Optimization via Conditional Discrete Diffusion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, Martin D. F. Wong
2023	J	`jnl`	A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun
2023	—	`conf`	APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning. ASP-DAC Ahmet Faruk Budak, David Smart, Brian Swahn, David Z. Pan
2023	J	`jnl`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2023	J	`jnl`	DOTA: A Dynamically-Operated Photonic Tensor Core for Energy-Efficient Transformer Accelerator. CoRR Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Zixuan Jiang, Zhekai Zhang, Rongxin Tang, Chenghao Feng, Song Han, Ray T. Chen, David Z. Pan
2023	J	`jnl`	DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints. CoRR Zhili Xiong, Rachel Selina Rajarathnam, Zhixing Jiang, Hanqing Zhu, David Z. Pan
2023	—	`conf`	DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. ISPD Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan
2023	—	`conf`	Delving into Effective Gradient Matching for Dataset Condensation. COINS Zixuan Jiang, Jiaqi Gu, Mingjie Liu, David Z. Pan
2023	J	`jnl`	ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan
2023	J	`jnl`	FPQA-C: A Compilation Framework for Field Programmable Qubit Array. CoRR Hanrui Wang, Pengyu Liu, Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han
2023	J	`jnl`	Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan
2023	A	`conf`	ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. DATE Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2023	J	`jnl`	Integrated multi-operand optical neurons for scalable and hardware-efficient deep learning. CoRR Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Rongxing Tang, Shupeng Ning, May Hlaing, Jason Midkiff, Sourabh Jain, David Z. Pan, Ray T. Chen
2023	J	`jnl`	Interactive Analog Layout Editing With Instant Placement and Routing Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang
2023	—	`conf`	Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities. ISPD Ahmet Faruk Budak, Keren Zhu, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia, David Z. Pan
2023	J	`jnl`	M3ICRO: Machine Learning-Enabled Compact Photonic Tensor Core based on PRogrammable Multi-Operand Multimode Interference. CoRR Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, David Z. Pan
2023	—	`conf`	NormSoftmax: Normalizing the Input of Softmax to Accelerate and Stabilize Training. COINS Zixuan Jiang, Jiaqi Gu, David Z. Pan
2023	J	`jnl`	PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems. IEEE Trans. Emerg. Top. Comput. Shaahin Angizi, Sepehr Tabrizchi, David Z. Pan, Arman Roohi
2023	J	`jnl`	Post-Layout Simulation Driven Analog Circuit Sizing. CoRR Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang
2023	A	`conf`	Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. ICCAD Ahmet Faruk Budak, Keren Zhu, David Z. Pan
2023	J	`jnl`	Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. CoRR Ahmet Faruk Budak, Keren Zhu, David Z. Pan
2023	A*	`conf`	Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers. NeurIPS Zixuan Jiang, Jiaqi Gu, Hanqing Zhu, David Z. Pan
2023	J	`jnl`	Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers. CoRR Zixuan Jiang, Jiaqi Gu, Hanqing Zhu, David Z. Pan
2023	Misc	`conf`	QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits. QCE Tianlong Chen, Zhenyu Zhang, Hanrui Wang, Jiaqi Gu, Zirui Li, David Z. Pan, Frederic T. Chong, Song Han, Zhangyang Wang
2023	—	`conf`	Reinforcement Learning Guided Detailed Routing for Custom Circuits. ISPD Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren
2023	J	`jnl`	RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training. CoRR Hanrui Wang, Yilian Liu, Pengyu Liu, Jiaqi Gu, Zirui Li, Zhiding Liang, Jinglei Cheng, Yongshan Ding, Xuehai Qian, Yiyu Shi, David Z. Pan, Frederic T. Chong, Song Han
2023	J	`jnl`	SqueezeLight: A Multi-Operand Ring-Based Optical Neural Network With Cross-Layer Scalability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan
2023	J	`jnl`	Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers. CoRR Hanrui Wang, Pengyu Liu, Kevin Shao, Dantong Li, Jiaqi Gu, David Z. Pan, Yongshan Ding, Song Han
2023	J	`jnl`	Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System. IEEE Trans. Circuits Syst. II Express Briefs Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan
2022	J	`jnl`	A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control. IEEE J. Solid State Circuits Ki Yong Kim, David Z. Pan, Ranjit Gharpurey
2022	—	`conf`	A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation. MLCAD Zixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, David Z. Pan
2022	A*	`conf`	A timing engine inspired graph neural network model for pre-routing slack prediction. DAC Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin
2022	A*	`conf`	ADEPT: automatic differentiable DEsign of photonic tensor cores. DAC Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, David Z. Pan
2022	J	`jnl`	An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design. CoRR Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Haoxing Ren
2022	J	`jnl`	An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu
2022	—	`conf`	AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. ISPD Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren
2022	—	`conf`	Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan
2022	—	`conf`	Challenges and Approaches in VLSI Routing. ISPD Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan
2022	—	`conf`	DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. ASP-DAC Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan
2022	J	`jnl`	Delving into Effective Gradient Matching for Dataset Condensation. CoRR Zixuan Jiang, Jiaqi Gu, Mingjie Liu, David Z. Pan
2022	—	`conf`	EDAML 2022 Keynote Speaker: Machine Learning for Agile, Intelligent and Open-Source EDA. IPDPS Workshops David Z. Pan
2022	—	`conf`	ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement. ASP-DAC Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan
2022	A	`conf`	Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. ICCAD Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan
2022	J	`jnl`	Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. CoRR Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan
2022	—	`conf`	Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan
2022	J	`jnl`	HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression. CoRR Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan
2022	J	`jnl`	Light in AI: Toward Efficient Neurocomputing With Optical Neural Networks - A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan
2022	J	`jnl`	MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel
2022	A*	`conf`	Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation. CVPR Jiaqi Gu, Hyoukjun Kwon, Dilin Wang, Wei Ye, Meng Li, Yu-Hsin Chen, Liangzhen Lai, Vikas Chandra, David Z. Pan
2022	A*	`conf`	NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation. NeurIPS Jiaqi Gu, Zhengqi Gao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, Duane S. Boning, David Z. Pan
2022	J	`jnl`	NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation. CoRR Jiaqi Gu, Zhengqi Gao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, Duane S. Boning, David Z. Pan
2022	J	`jnl`	On-chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks. CoRR Hanrui Wang, Zirui Li, Jiaqi Gu, Yongshan Ding, David Z. Pan, Song Han
2022	A*	`conf`	QOC: quantum on-chip training with parameter shift and gradient pruning. DAC Hanrui Wang, Zirui Li, Jiaqi Gu, Yongshan Ding, David Z. Pan, Song Han
2022	J	`jnl`	QuEst: Graph Transformer for Quantum Circuit Reliability Estimation. CoRR Hanrui Wang, Pengyu Liu, Jinglei Cheng, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding, Weiwen Jiang, Yiyu Shi, Xuehai Qian, David Z. Pan, Frederic T. Chong, Song Han
2022	A*	`conf`	QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits. HPCA Hanrui Wang, Yongshan Ding, Jiaqi Gu, Yujun Lin, David Z. Pan, Frederic T. Chong, Song Han
2022	A*	`conf`	QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization. DAC Hanrui Wang, Jiaqi Gu, Yongshan Ding, Zirui Li, Frederic T. Chong, David Z. Pan, Song Han
2022	—	`conf`	Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). ASP-DAC Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan
2022	J	`jnl`	Rethinking Graph Neural Networks for the Graph Coloring Problem. CoRR Wei Li, Ruxuan Li, Yuzhe Ma, Siu On Chan, David Z. Pan, Bei Yu
2022	—	`conf`	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. MLCAD Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun
2022	J	`jnl`	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. CoRR Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun
2022	A	`conf`	Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories. DATE Hao Chen, Walker J. Turner, David Z. Pan, Haoxing Ren
2022	J	`jnl`	TAG: Learning Circuit Spatial Embedding From Layouts. CoRR Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren
2022	A	`conf`	TAG: Learning Circuit Spatial Embedding from Layouts. ICCAD Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren
2022	A	`conf`	TorchQuantum Case Study for Robust Quantum Circuits. ICCAD Hanrui Wang, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding, Weiwen Jiang, Yiyu Shi, David Z. Pan, Frederic T. Chong, Song Han
2022	J	`jnl`	elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibai Meng, Wuxi Li, Yibo Lin, David Z. Pan
2021	—	`conf`	A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun
2021	J	`jnl`	A New Acceleration Paradigm for Discrete CosineTransform and Other Fourier-Related Transforms. CoRR Zixuan Jiang, Jiaqi Gu, David Z. Pan
2021	J	`jnl`	A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2021	—	`conf`	ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection. MLCAD Mohamed Baker Alawieh, David Z. Pan
2021	J	`jnl`	ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores. CoRR Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, David Z. Pan
2021	—	`conf`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2021	A*	`conf`	DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. DAC Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap
2021	J	`jnl`	DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. CoRR Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap
2021	J	`jnl`	DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan
2021	—	`conf`	Delving into Macro Placement with Reinforcement Learning. MLCAD Zixuan Jiang, Ebrahim M. Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, Joe W. J. Jiang, Young-Joon Lee, David Z. Pan
2021	J	`jnl`	Delving into Macro Placement with Reinforcement Learning. CoRR Zixuan Jiang, Ebrahim M. Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, Joe W. J. Jiang, Young-Joon Lee, David Z. Pan
2021	J	`jnl`	ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement. CoRR Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan
2021	A*	`conf`	Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization. AAAI Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Ray T. Chen, David Z. Pan
2021	J	`jnl`	GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan
2021	A*	`conf`	Interactive Analog Layout Editing with Instant Placement Legalization. DAC Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin
2021	A*	`conf`	L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization. NeurIPS Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, David Z. Pan
2021	J	`jnl`	L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization. CoRR Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, David Z. Pan
2021	—	`conf`	Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. ASP-DAC Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	—	`conf`	MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan
2021	J	`jnl`	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
2021	J	`jnl`	Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation. CoRR Jiaqi Gu, Hyoukjun Kwon, Dilin Wang, Wei Ye, Meng Li, Yu-Hsin Chen, Liangzhen Lai, Vikas Chandra, David Z. Pan
2021	A	`conf`	O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands. DATE Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Ray T. Chen, David Z. Pan
2021	J	`jnl`	OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2021	A	`conf`	OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan
2021	J	`jnl`	Optimizer Fusion: Efficient Training with Better Locality and Parallelism. CoRR Zixuan Jiang, Jiaqi Gu, Mingjie Liu, Keren Zhu, David Z. Pan
2021	A	`conf`	Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. DATE Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren
2021	J	`jnl`	QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits. CoRR Hanrui Wang, Yongshan Ding, Jiaqi Gu, Yujun Lin, David Z. Pan, Frederic T. Chong, Song Han
2021	J	`jnl`	RoQNN: Noise-Aware Training for Robust Quantum Neural Networks. CoRR Hanrui Wang, Jiaqi Gu, Yongshan Ding, Zirui Li, Frederic T. Chong, David Z. Pan, Song Han
2021	J	`jnl`	Silicon photonic subspace neural chip for hardware-efficient deep learning. CoRR Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David Z. Pan, Ray T. Chen
2021	A	`conf`	SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators. DATE Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan
2021	J	`jnl`	Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan
2021	A*	`conf`	Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation. ICCV Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan
2021	J	`jnl`	Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation. CoRR Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan
2021	A*	`conf`	Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun
2020	J	`jnl`	A 0.025-mm IEEE J. Solid State Circuits Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2020	J	`jnl`	A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
2020	J	`jnl`	ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan
2020	—	`conf`	An Efficient Training Framework for Reversible Neural Architectures. ECCV (27) Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu, David Z. Pan
2020	J	`jnl`	An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun
2020	J	`jnl`	An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun
2020	J	`jnl`	An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits Shaolan Li, David Z. Pan, Nan Sun
2020	A*	`conf`	Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan
2020	A	`conf`	DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints. ICCAD Jiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan
2020	A	`conf`	Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	J	`jnl`	Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization. CoRR Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Ray T. Chen, David Z. Pan
2020	—	`conf`	Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. MLCAD Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan
2020	A*	`conf`	FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization. DAC Jiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen, David Z. Pan
2020	—	`conf`	High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	—	`conf`	ML for CAD - Where is the Treasure Hiding? MLCAD Raviv Gal, David Z. Pan, Haoxing Ren, Manish Pandey, Marilyn Wolf, Avi Ziv
2020	J	`jnl`	Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks. IEEE Access Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo, David Z. Pan
2020	A	`conf`	ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls. DATE Jiaqi Gu, Zheng Zhao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan
2020	A	`conf`	Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk). ICCAD Mohamed Baker Alawieh, Wei Ye, David Z. Pan
2020	—	`conf`	ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist. HOST Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, David Z. Pan
2020	J	`jnl`	Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019). IEEE Des. Test David Z. Pan
2020	—	`conf`	S ASP-DAC Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A*	`conf`	SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures. DAC Navid Khoshavi, Arman Roohi, Connor Broyles, Saman Sargolzaei, Yu Bi, David Z. Pan
2020	J	`jnl`	Semisupervised Hotspot Detection With Self-Paced Multitask Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan
2020	—	`conf`	TEMPO: Fast Mask Topography Effect Modeling with Deep Learning. ISPD Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan
2020	J	`jnl`	TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020	J	`jnl`	TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann
2020	A	`conf`	Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture. ASP-DAC Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan
2020	A	`conf`	Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020	J	`jnl`	Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. Taehyun Kwon, Muhammad Imran, David Z. Pan, Joon-Sung Yang
2020	A*	`conf`	Wafer Map Defect Patterns Classification using Deep Selective Learning. DAC Mohamed Baker Alawieh, Duane S. Boning, David Z. Pan
2019	—	`conf`	A 0.025-mm CICC Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2019	—	`conf`	A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC Shaolan Li, Biying Xu, David Z. Pan, Nan Sun
2019	J	`jnl`	A New Paradigm for FPGA Placement Without Explicit Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wuxi Li, David Z. Pan
2019	J	`jnl`	A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2019	—	`conf`	A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019	A*	`conf`	DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. DAC Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan
2019	J	`jnl`	Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan
2019	A	`conf`	Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper. ICCAD Zheng Zhao, Jiaqi Gu, Zhoufeng Ying, Chenghao Feng, Ray T. Chen, David Z. Pan
2019	—	`conf`	Device Layer-Aware Analytical Placement for Analog Circuits. ISPD Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
2019	A	`conf`	Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis. DATE Zheng Zhao, Derong Liu, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen, David Z. Pan
2019	B	`conf`	FPGA Accelerated FPGA Placement. FPL Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019	—	`conf`	FPGA-Accelerated Spreading for Global Placement. HPEC Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019	A*	`conf`	GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks. DAC Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan
2019	A	`conf`	GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	—	`conf`	Hardware-software co-design of slimmed optical neural networks. ASP-DAC Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan
2019	J	`jnl`	IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview. ACM Trans. Design Autom. Electr. Syst. Kaveh Shamsi, Meng Li, Kenneth Plaks, Saverio Fazzari, David Z. Pan, Yier Jin
2019	A	`conf`	IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits. ICCAD Kaveh Shamsi, David Z. Pan, Yier Jin
2019	A	`conf`	KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation. DATE Kaveh Shamsi, Meng Li, David Z. Pan, Yier Jin
2019	A	`conf`	Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection. DATE Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, David Z. Pan
2019	A*	`conf`	LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. DAC Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan
2019	—	`conf`	LithoROC: lithography hotspot detection with explicit ROC optimization. ASP-DAC Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan
2019	A	`conf`	MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A	`conf`	Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning. ICCAD Chengyue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan
2019	J	`jnl`	On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes. IEEE Trans. Inf. Forensics Secur. Kaveh Shamsi, Travis Meade, Meng Li, David Z. Pan, Yier Jin
2019	—	`conf`	On the Impossibility of Approximation-Resilient Circuit Locking. HOST Kaveh Shamsi, David Z. Pan, Yier Jin
2019	—	`conf`	OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2019	A	`ed.`	Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019 ICCAD David Z. Pan
2019	J	`jnl`	Provably Secure Camouflaging Strategy for IC Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan
2019	A*	`conf`	Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models. DAC Mohamed Baker Alawieh, Sinead A. Williamson, David Z. Pan
2019	—	`conf`	S ASP-DAC Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan
2019	—	`conf`	Semi-supervised hotspot detection with self-paced multi-task learning. ASP-DAC Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan
2019	A	`conf`	Simultaneous Placement and Clock Tree Construction for Modern FPGAs. FPGA Wuxi Li, Mehrdad E. Dehkordi, Stephen Yang, David Z. Pan
2019	J	`jnl`	Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan
2019	—	`conf`	Tackling signal electromigration with learning-based detection and multistage mitigation. ASP-DAC Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan
2019	A*	`conf`	WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2019	A	`conf`	elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. ICCAD Wuxi Li, Yibo Lin, David Z. Pan
2018	J	`jnl`	A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun
2018	—	`conf`	A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. ASP-DAC Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2018	—	`conf`	Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting. ISPD Biying Xu, Bülent Basaran, Ming Su, David Z. Pan
2018	J	`jnl`	Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taehee Lee, David Z. Pan, Joon-Sung Yang
2018	J	`jnl`	Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test Sri Parameswaran, R. Iris Bahar, David Z. Pan
2018	—	`conf`	Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures. ACM Great Lakes Symposium on VLSI Kaveh Shamsi, Meng Li, David Z. Pan, Yier Jin
2018	J	`jnl`	Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng
2018	—	`conf`	Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning. ISPD Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan
2018	J	`jnl`	Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection. CoRR Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan
2018	—	`conf`	GDP: GPU accelerated Detailed Placement. HPEC Shounak Dhar, David Z. Pan
2018	J	`jnl`	Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP. IEEE Trans. Very Large Scale Integr. Syst. Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu
2018	J	`jnl`	Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng
2018	J	`jnl`	Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, Meng Li, David Z. Pan
2018	—	`conf`	Layout-dependent aging mitigation for critical path timing. ASP-DAC Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan
2018	—	`conf`	Logic synthesis for energy-efficient photonic integrated circuits. ASP-DAC Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan
2018	A	`conf`	Machine Learning for Yield Learning and Optimization. ITC Yibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan
2018	—	`conf`	Machine learning for IC design and technology co-optimization in extreme scaling. VLSI-DAT David Z. Pan
2018	J	`jnl`	MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2018	A*	`conf`	OPERON: optical-electrical power-efficient route synthesis for on-chip signals. DAC Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan
2018	J	`jnl`	OpenMPL: An Open Source Layout Decomposer. CoRR Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2018	—	`conf`	Power Grid Reduction by Sparse Convex Optimization. ISPD Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan
2018	J	`jnl`	Subresolution Assist Feature Generation With Supervised Data Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan
2018	J	`jnl`	TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
2018	J	`jnl`	Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng
2018	A	`conf`	TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann
2018	A	`conf`	TimingSAT: Decamouflaging Timing-based Logic Obfuscation. ITC Meng Li, Kaveh Shamsi, Yier Jin, David Z. Pan
2018	J	`jnl`	UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine. ACM Trans. Design Autom. Electr. Syst. Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan
2018	J	`jnl`	UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wuxi Li, Shounak Dhar, David Z. Pan
2017	A*	`conf`	A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC Biying Xu, Shaolan Li, Nan Sun, David Z. Pan
2017	J	`jnl`	An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng
2017	—	`conf`	An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan
2017	—	`conf`	AppSAT: Approximately deobfuscating integrated circuits. HOST Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin
2017	—	`conf`	Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail? ACM Great Lakes Symposium on VLSI Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin
2017	A*	`conf`	Concurrent Pin Access Optimization for Unidirectional Routing. DAC Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan
2017	A*	`conf`	Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack. DAC Meng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan
2017	—	`conf`	Cyclic Obfuscation for Creating SAT-Unresolvable Circuits. ACM Great Lakes Symposium on VLSI Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin
2017	—	`conf`	DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. ISPD Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan
2017	C	`conf`	DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. ICCD Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan
2017	—	`conf`	Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan
2017	J	`jnl`	High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, David Z. Pan
2017	J	`jnl`	Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos
2017	J	`jnl`	Incremental Layer Assignment for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
2017	—	`conf`	Optical computing on silicon-on-insulator-based photonic integrated circuits. ASICON Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan
2017	C	`conf`	Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
2017	A	`conf`	Placement mitigation techniques for power grid electromigration. ISLPED Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan, David Z. Pan
2017	J	`jnl`	PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control. CoRR Meng Li, Liangzhen Lai, Naveen Suda, Vikas Chandra, David Z. Pan
2017	J	`jnl`	Redundant Local-Loop Insertion for Unidirectional Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan
2017	C	`conf`	Revisit sequential logic obfuscation: Attacks and defenses. ISCAS Travis Meade, Zheng Zhao, Shaojie Zhang, David Z. Pan, Yier Jin
2017	J	`jnl`	Stitch aware detailed placement for multiple E-beam lithography. Integr. Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2017	A*	`conf`	Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. DAC Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan
2017	J	`jnl`	Toward Unidirectional Routing Closure in Advanced Technology Nodes. IPSJ Trans. Syst. LSI Des. Methodol. Xiaoqing Xu, David Z. Pan
2017	J	`jnl`	Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2017	A	`conf`	UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper). ICCAD Wuxi Li, Meng Li, Jiajun Wang, David Z. Pan
2016	—	`conf`	A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation. ISPD Xiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan
2016	A	`conf`	A novel unified dummy fill insertion framework with SQP-based optimization method. ICCAD Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2016	—	`conf`	Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography. ISPD Jiaojiao Ou, Bei Yu, David Z. Pan
2016	J	`jnl`	Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
2016	A	`conf`	Detailed placement for modern FPGAs using 2D dynamic programming. ICCAD Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan
2016	J	`jnl`	EBL Overlapping Aware Stencil Planning for MCC System. ACM Trans. Design Autom. Electr. Syst. Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan
2016	—	`ch.`	Global Routing. Encyclopedia of Algorithms Minsik Cho, David Z. Pan
2016	A*	`conf`	Incremental layer assignment for critical path timing. DAC Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan
2016	—	`conf`	Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC. ASP-DAC Tetsuaki Matsunawa, Bei Yu, David Z. Pan
2016	J	`jnl`	Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng
2016	—	`ch.`	Layout Decomposition for Triple Patterning. Encyclopedia of Algorithms Bei Yu, David Z. Pan
2016	A	`conf`	MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	J	`jnl`	OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan
2016	J	`jnl`	PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. ACM Trans. Design Autom. Electr. Syst. Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan
2016	J	`jnl`	Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2016	A*	`conf`	Practical public PUF enabled by solving max-flow problem on chip. DAC Meng Li, Jin Miao, Kai Zhong, David Z. Pan
2016	A	`conf`	Provably secure camouflaging strategy for IC protection. ICCAD Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan
2016	—	`conf`	Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	A	`conf`	UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing. ICCAD Wuxi Li, Shounak Dhar, David Z. Pan
2015	C	`conf`	CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen
2015	J	`jnl`	Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
2015	—	`conf`	Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design. ACM Great Lakes Symposium on VLSI Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov
2015	J	`jnl`	E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System. CoRR Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan
2015	—	`conf`	Electromigration-aware redundant via insertion. ASP-DAC Jiwoo Pak, Bei Yu, David Z. Pan
2015	A*	`conf`	High performance dummy fill insertion with coupling and uniformity constraints. DAC Yibo Lin, Bei Yu, David Z. Pan
2015	A*	`conf`	High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. DAC Keith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen
2015	J	`jnl`	Layout Decomposition for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bei Yu, Kun Yuan, Duo Ding, David Z. Pan
2015	J	`jnl`	Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng
2015	—	`conf`	Machine learning and pattern matching in physical design. ASP-DAC Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng
2015	J	`jnl`	Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan
2015	A*	`conf`	OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan
2015	A*	`conf`	PARR: pin access planning and regular routing for self-aligned double patterning. DAC Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan
2015	—	`conf`	Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2015	A*	`conf`	Pushing multiple patterning in sub-10nm: are we ready? DAC David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin
2015	J	`jnl`	Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2015	—	`conf`	Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet
2015	—	`conf`	Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line. ACM Great Lakes Symposium on VLSI Wei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann
2015	A	`conf`	TILA: Timing-Driven Incremental Layer Assignment. ICCAD Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan
2015	A	`conf`	Toward Metrics of Design Automation Research Impact. ICCAD Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins
2015	A	`conf`	Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. ICCAD Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2014	J	`jnl`	A High-Performance Triple Patterning Layout Decomposer with Balanced Density. CoRR Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan
2014	—	`conf`	BOB-router: A new buffering-aware global router with over-the-block routing resources optimization. ASP-DAC Yilin Zhang, Salim Chowdhury, David Z. Pan
2014	—	`conf`	Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
2014	J	`jnl`	E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System. CoRR Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan
2014	J	`jnl`	EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. CoRR Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan
2014	J	`jnl`	Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond. ACM Trans. Design Autom. Electr. Syst. Naehyuck Chang, David Z. Pan, Yuan Xie
2014	J	`jnl`	Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiwoo Pak, Sung Kyu Lim, David Z. Pan
2014	J	`jnl`	GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. CoRR Duo Ding, Bei Yu, David Z. Pan
2014	J	`jnl`	L-Shape based Layout Fracturing for E-Beam Lithography. CoRR Bei Yu, Jhih-Rong Gao, David Z. Pan
2014	A*	`conf`	Layout Decomposition for Quadruple Patterning Lithography and Beyond. DAC Bei Yu, David Z. Pan
2014	J	`jnl`	Layout Decomposition for Quadruple Patterning Lithography and Beyond. CoRR Bei Yu, David Z. Pan
2014	J	`jnl`	Layout decomposition for triple patterning lithography. CoRR Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan
2014	J	`jnl`	Lithography Hotspot Detection and Mitigation in Nanometer VLSI. CoRR Jhih-Rong Gao, Bei Yu, David Z. Pan
2014	A*	`conf`	MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction. DAC Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan
2014	J	`jnl`	Methodology for standard cell compliance and detailed placement for triple patterning lithography. CoRR Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan
2014	Misc	`conf`	Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. VLSID Subhendu Roy, David Z. Pan
2014	J	`jnl`	Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement. CoRR Jhih-Rong Gao, Bei Yu, Ru Huang, David Z. Pan
2014	—	`conf`	Self-aligned double patterning aware pin access and standard cell layout co-optimization. ISPD Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan
2014	—	`conf`	Self-aligned double patterning layout decomposition with complementary e-beam lithography. ASP-DAC Jhih-Rong Gao, Bei Yu, David Z. Pan
2014	J	`jnl`	TRIAD: a triple patterning lithography aware detailed router. CoRR Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li
2014	J	`jnl`	TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. Commun. ACM Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
2014	—	`conf`	Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints. ISPD Yilin Zhang, David Z. Pan
2014	J	`jnl`	Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2014	J	`jnl`	Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). CoRR Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan
2014	J	`jnl`	Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting. CoRR Bei Yu, Jhih-Rong Gao, David Z. Pan
2013	A	`conf`	A high-performance triple patterning layout decomposer with balanced density. ICCAD Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan
2013	A*	`conf`	An accurate semi-analytical framework for full-chip TSV-induced stress modeling. DAC Yang Li, David Z. Pan
2013	J	`jnl`	Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wooyoung Jang, David Z. Pan
2013	J	`jnl`	Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Moongon Jung, David Z. Pan, Sung Kyu Lim
2013	A	`conf`	Clock power minimization using structured latch templates and decision tree induction. ICCAD Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan
2013	J	`jnl`	Design for Manufacturing With Emerging Nanolithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Z. Pan, Bei Yu, Jhih-Rong Gao
2013	A*	`conf`	E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. DAC Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan
2013	A	`conf`	Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs. ICCAD Jiwoo Pak, Sung Kyu Lim, David Z. Pan
2013	J	`jnl`	Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
2013	—	`conf`	L-shape based layout fracturing for e-beam lithography. ASP-DAC Bei Yu, Jhih-Rong Gao, David Z. Pan
2013	—	`conf`	Lithography hotspot detection and mitigation in nanometer VLSI. ASICON Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan
2013	A	`conf`	Methodology for standard cell compliance and detailed placement for triple patterning lithography. ICCAD Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan
2013	J	`jnl`	Skew Management of NBTI Impacted Gated Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashutosh Chakraborty, David Z. Pan
2013	J	`jnl`	Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2013	A*	`conf`	Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2012	J	`jnl`	A3MAP: Architecture-aware analytic mapping for networks-on-chip. ACM Trans. Design Autom. Electr. Syst. Wooyoung Jang, David Z. Pan
2012	J	`jnl`	An accurate sparse-matrix based framework for statistical static timing analysis. Integr. Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan
2012	A*	`conf`	Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. DAC Moongon Jung, David Z. Pan, Sung Kyu Lim
2012	A	`conf`	Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan
2012	—	`conf`	Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang
2012	J	`jnl`	E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun Yuan, Bei Yu, David Z. Pan
2012	—	`conf`	EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. ASP-DAC Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan
2012	A	`conf`	Electromigration-aware routing for 3D ICs with stress-aware EM modeling. ICCAD Jiwoo Pak, Sung Kyu Lim, David Z. Pan
2012	—	`conf`	Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. ISPD Jhih-Rong Gao, David Z. Pan
2012	—	`conf`	GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. ASP-DAC Duo Ding, Bei Yu, David Z. Pan
2012	—	`conf`	Keep it straight: teaching placement how to better handle designs with datapaths. ISPD Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2012	A*	`conf`	PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning. DAC Samuel I. Ward, Duo Ding, David Z. Pan
2012	A	`conf`	Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. ICCAD Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan
2012	—	`conf`	Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
2012	A	`conf`	TRIAD: A triple patterning lithography aware detailed router. ICCAD Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li
2012	J	`jnl`	TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
2012	J	`jnl`	UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan
2012	—	`conf`	VLSI CAD for emerging nanolithography. VLSI-DAT David Z. Pan, Jhih-Rong Gao, Bei Yu
2011	J	`jnl`	A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip. IEEE J. Emerg. Sel. Topics Circuits Syst. Wooyoung Jang, David Z. Pan
2011	A*	`conf`	AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection. DAC Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
2011	J	`jnl`	Application-Aware NoC Design for Efficient SDRAM Access. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wooyoung Jang, David Z. Pan
2011	—	`conf`	CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli
2011	A	`conf`	Chemical-mechanical polishing aware application-specific 3D NoC design. ICCAD Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan
2011	—	`conf`	Controlling NBTI degradation during static burn-in testing. ASP-DAC Ashutosh Chakraborty, David Z. Pan
2011	A	`conf`	Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li
2011	—	`conf`	E-beam lithography stencil planning and optimization with overlapped characters. ISPD Kun Yuan, David Z. Pan
2011	A	`conf`	Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. ICCAD Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim
2011	—	`conf`	Exploration of VLSI CAD researches for early design rule evaluation. ASP-DAC Chul-Hong Park, David Z. Pan, Kevin Lucas
2011	A*	`conf`	Flexible 2D layout decomposition framework for spacer-type double pattering lithography. DAC Yongchan Ban, Kevin Lucas, David Z. Pan
2011	A	`conf`	Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. ICCAD Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim
2011	J	`jnl`	High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Duo Ding, J. Andres Torres, David Z. Pan
2011	—	`conf`	High performance lithographic hotspot detection using hierarchically refined machine learning. ASP-DAC Duo Ding, Andres J. Torres, Fedor G. Pikus, David Z. Pan
2011	A	`conf`	Layout decomposition for triple patterning lithography. ICCAD Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan
2011	J	`jnl`	Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization. IEEE J. Emerg. Sel. Topics Circuits Syst. Yongchan Ban, David Z. Pan
2011	J	`jnl`	Robust Chip-Level Clock Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Rajaram, David Z. Pan
2011	—	`conf`	Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan
2011	A*	`conf`	TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. DAC Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
2010	—	`conf`	A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. ASP-DAC Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan
2010	—	`conf`	A3MAP: architecture-aware analytic mapping for networks-on-chip. ASP-DAC Wooyoung Jang, David Z. Pan
2010	J	`jnl`	An SDRAM-Aware Router for Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wooyoung Jang, David Z. Pan
2010	A*	`conf`	Application-aware NoC design for efficient SDRAM access. DAC Wooyoung Jang, David Z. Pan
2010	A*	`conf`	Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. DAC Yongchan Ban, David Z. Pan
2010	J	`jnl`	Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun Yuan, Jae-Seok Yang, David Z. Pan
2010	J	`jnl`	Manufacturability Aware Routing in Nanometer VLSI. Found. Trends Electron. Des. Autom. David Z. Pan, Minsik Cho, Kun Yuan
2010	J	`jnl`	MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Rajaram, David Z. Pan
2010	A	`conf`	Novel binary linear programming for high performance clock mesh synthesis. ICCAD Minsik Cho, David Z. Pan, Ruchir Puri
2010	A	`conf`	PASAP: power aware structured ASIC placement. ISLPED Ashutosh Chakraborty, David Z. Pan
2010	—	`conf`	Skew management of NBTI impacted gated clock trees. ISPD Ashutosh Chakraborty, David Z. Pan
2010	J	`jnl`	Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
2010	A	`conf`	Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
2010	A*	`conf`	TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan
2010	—	`conf`	Total sensitivity based dfm optimization of standard library cells. ISPD Yongchan Ban, Savithri Sundareswaran, David Z. Pan
2010	A	`conf`	WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography. ICCAD Kun Yuan, David Z. Pan
2009	A*	`conf`	An SDRAM-aware router for Networks-on-Chip. DAC Wooyoung Jang, David Z. Pan
2009	A	`conf`	Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan
2009	J	`jnl`	BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. ACM Trans. Design Autom. Electr. Syst. Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan
2009	—	`conf`	Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD Kun Yuan, Jae-Seok Yang, David Z. Pan
2009	A*	`conf`	Double patterning lithography friendly detailed routing with redundant via consideration. DAC Kun Yuan, Katrina Lu, David Z. Pan
2009	J	`jnl`	ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
2009	A*	`conf`	O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. DAC Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan
2009	—	`conf`	OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. SLIP Duo Ding, David Z. Pan
2009	—	`conf`	On stress aware active area sizing, gate sizing, and repeater insertion. ISPD Ashutosh Chakraborty, David Z. Pan
2009	A*	`conf`	RegPlace: a high quality open-source placement framework for structured ASICs. DAC Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
2008	J	`jnl`	A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minsik Cho, David Z. Pan
2008	—	`conf`	A high-performance droplet router for digital microfluidic biochips. ISPD Minsik Cho, David Z. Pan
2008	A	`conf`	A voltage-frequency island aware energy optimization framework for networks-on-chip. ICCAD Wooyoung Jang, Duo Ding, David Z. Pan
2008	A*	`conf`	An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
2008	—	`conf`	DPlace2.0: A stable and efficient analytical placement based on diffusion. ASP-DAC Tao Luo, David Z. Pan
2008	A	`conf`	Double patterning technology friendly detailed routing. ICCAD Minsik Cho, Yongchan Ban, David Z. Pan
2008	A*	`conf`	ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. DAC Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
2008	J	`jnl`	Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. IEEE Trans. Very Large Scale Integr. Syst. Minsik Cho, David Z. Pan
2008	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Patrick H. Madden, David Z. Pan
2008	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Z. Pan, Gi-Joon Nam
2008	A	`conf`	Latch Modeling for Statistical Timing Analysis. DATE Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan
2008	A	`conf`	Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
2008	—	`conf`	Lithography friendly routing: from construct-by-correction to correct-by-construction. SBCCI David Z. Pan
2008	—	`ch.`	Manufacturability-Aware Routing. Handbook of Algorithms for Physical Design Automation Minsik Cho, Joydeep Mitra, David Z. Pan
2008	—	`conf`	MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC Anand Rajaram, David Z. Pan
2008	J	`jnl`	Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
2008	—	`conf`	Metal-density driven placement for cmp variation and routability. ISPD Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
2008	A	`conf`	Nanolithography and CAD challenges for 32nm/22nm and beyond. ICCAD David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay
2008	A	`conf`	Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD Jae-Seok Yang, David Z. Pan
2008	—	`ed.`	Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008 ISPD David Z. Pan, Gi-Joon Nam
2008	A	`conf`	Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan
2008	A*	`conf`	Robust chip-level clock tree synthesis for SOC designs. DAC Anand Rajaram, David Z. Pan
2008	—	`conf`	Synergistic modeling and optimization for nanometer IC design/manufacturing integration. SBCCI David Z. Pan
2008	—	`conf`	Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. ASP-DAC David Z. Pan, Minsik Cho
2008	—	`conf`	Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock. BIBM Peng Yu, Xi Chen, David Z. Pan, Andrew D. Ellington
2008	—	`ch.`	Timing-Driven Placement. Handbook of Algorithms for Physical Design Automation David Z. Pan, Bill Halpin, Haoxing Ren
2008	—	`conf`	Total power optimization combining placement, sizing and multi-Vt through slack distribution management. ASP-DAC Tao Luo, David Newmark, David Z. Pan
2008	J	`jnl`	Track Routing and Optimization for Yield. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
2007	A	`conf`	A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. ICCAD Peng Yu, David Z. Pan
2007	A*	`conf`	Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
2007	—	`conf`	Accurate power grid analysis with behavioral transistor network modeling. ISPD Anand Ramalingam, Giri Devarayanadurg, David Z. Pan
2007	A	`conf`	BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. ICCAD Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan
2007	J	`jnl`	BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Minsik Cho, David Z. Pan
2007	—	`ch.`	DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective. Modern Circuit Placement Tao Luo, David Z. Pan
2007	J	`jnl`	Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam
2007	—	`conf`	Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
2007	—	`conf`	ISPD placement contest updates and ISPD 2007 global routing contest. ISPD Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden
2007	—	`ed.`	Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 ISPD Patrick H. Madden, David Z. Pan
2007	—	`conf`	Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
2007	A	`conf`	TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. ICCAD Peng Yu, David Z. Pan
2007	A*	`conf`	TROY: Track Router with Yield-driven Wire Planning. DAC Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
2007	J	`jnl`	Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electron. Anand Ramalingam, Anirudh Devgan, David Z. Pan
2006	A*	`conf`	A new LP based incremental timing driven placement for high performance designs. DAC Tao Luo, David Newmark, David Z. Pan
2006	A	`conf`	A unified non-rectangular device and circuit simulation model for timing and power. ICCAD Sean X. Shi, Peng Yu, David Z. Pan
2006	—	`conf`	Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
2006	A	`conf`	An accurate sparse matrix based framework for statistical static timing analysis. ICCAD Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
2006	A*	`conf`	BoxRouter: a new global router based on box expansion and progressive ILP. DAC Minsik Cho, David Z. Pan
2006	—	`conf`	Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED Anand Rajaram, David Z. Pan
2006	—	`conf`	Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. ASP-DAC Minsik Cho, Hongjoong Shin, David Z. Pan
2006	Misc	`conf`	PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. VTS Minsik Cho, David Z. Pan
2006	C	`conf`	Partial Functional Manipulation Based Wirelength Minimization. ICCD Avijit Dutta, David Z. Pan
2006	A*	`conf`	Process variation aware OPC with variational lithography modeling. DAC Peng Yu, Sean X. Shi, David Z. Pan
2006	—	`conf`	Robust analytical gate delay modeling for low voltage circuits. ASP-DAC Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
2006	—	`conf`	Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ISQED Andrew Havlir, David Z. Pan
2006	—	`conf`	Variation tolerant buffered clock network synthesis with cross links. ISPD Anand Rajaram, David Z. Pan
2006	A	`conf`	Wire density driven global routing for CMP variation and timing. ICCAD Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
2006	—	`conf`	Wire sizing with scattering effect for nanoscale interconnection. ASP-DAC Sean X. Shi, David Z. Pan
2005	—	`conf`	CMP aware shuttle mask floorplanning. ASP-DAC Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong
2005	—	`conf`	Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD Anand Rajaram, David Z. Pan, Jiang Hu
2005	—	`conf`	Redundant-via enhanced maze routing for yield improvement. ASP-DAC Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
2005	—	`conf`	Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
2005	A	`conf`	TACO: temperature aware clock-tree optimization. ICCAD Minsik Cho, Suhail Ahmed, David Z. Pan
2003	A*	`conf`	Pushing ASIC performance in a power envelope. DAC Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni