David M. Lewis

51 papers A* 2A 16B 2C 5Misc 2Journal 18Unranked 6

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David M. Lewis, Herman Schmit
2017	—	`conf`	3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. ISSCC David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay
2016	A	`conf`	Stratix™ 10 High Performance Routable Clock Networks. FPGA Carl Ebeling, Dana How, David M. Lewis, Herman Schmit
2016	A	`conf`	The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken
2015	—	`conf`	Arria™ 10 device architecture. CICC Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang
2013	A	`conf`	Architectural enhancements in Stratix V™. FPGA David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu
2011	J	`jnl`	An Empirical Evaluation of Similarity Coefficients for Binary Valued Data. Int. J. Data Warehous. Min. David M. Lewis, Vandana Pursnani Janeja
2010	A	`conf`	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz
2009	A	`conf`	Architectural enhancements in Stratix-III FPGA David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan
2005	A	`conf`	The Stratix II logic and routing architecture. FPGA David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
2004	B	`conf`	Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini
2004	—	`conf`	MAX II: A low-cost, high-performance LUT-based CPLD. CICC Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis
2003	—	`conf`	Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. CICC Andy Gean Ye, Jonathan Rose, David M. Lewis
2003	—	`conf`	Cyclone ™: a low-cost, high-performance FPGA. CICC Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello
2003	A	`conf`	The Stratix FPGA David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
2002	B	`conf`	Analytical Framework for Switch Block Design. FPL Guy G. Lemieux, David M. Lewis
2002	A	`conf`	Circuit design of routing switches. FPGA Guy G. Lemieux, David M. Lewis
2002	—	`conf`	Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT Andy Gean Ye, Jonathan Rose, David M. Lewis
2001	A	`conf`	Using sparse crossbars within LUT. FPGA Guy G. Lemieux, David M. Lewis
2000	Misc	`conf`	Design of a VLIW Compute Accelerator on the Transmogrifier-2. FCCM L. Louis Zhang, Qiang Wang, David M. Lewis
2000	A	`conf`	Generating highly-routable sparse crossbars for PLDs. FPGA Guy G. Lemieux, Paul Leventis, David M. Lewis
1999	A	`conf`	Procedural Texture Mapping on FPGAs. FPGA Andy Gean Ye, David M. Lewis
1998	J	`jnl`	The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. Very Large Scale Integr. Syst. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1997	Misc	`conf`	Automated field-programmable compute accelerator design using partial evaluation. FCCM Qiang Wang, David M. Lewis
1997	A	`conf`	The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1996	A	`conf`	Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. FPGA Vi Cuong Chan, David M. Lewis
1996	J	`jnl`	Atmospheric diffusion: some new mathematical models. Adv. Comput. Math. P. C. Chatwin, David M. Lewis, Nils Mole
1996	J	`jnl`	DP-FPGA: An FPGA Architecture Optimized for Datapaths. VLSI Design Don Cherepacha, David M. Lewis
1995	J	`jnl`	114 MFLOPS logarithmic number system arithmetic unit for DSP applications. IEEE J. Solid State Circuits David M. Lewis
1994	J	`jnl`	Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. IEEE Trans. Computers David M. Lewis
1994	C	`conf`	Routing Architectures for Hierarchical Field Programmable Gate Arrays. ICCD Aditya A. Aggarwal, David M. Lewis
1993	C	`conf`	A Field Programmable Accelerator for Compiled-Code Applications. ICCD David M. Lewis, Marcus van Ierssel, Daniel H. Wong
1993	J	`jnl`	A multiple-strength multiple-delay compiled-code logic simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahmet N. Parlakbilek, David M. Lewis
1993	C	`conf`	An accurate LNS arithmetic unit using interleaved memory function interpolator. IEEE Symposium on Computer Arithmetic David M. Lewis
1993	C	`conf`	Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. ISCAS David A. Johns, David M. Lewis, Don Cherepacha
1992	J	`jnl`	A compiled-code hardware accelerator for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David M. Lewis
1992	J	`jnl`	The effect of logic block architecture on FPGA performance. IEEE J. Solid State Circuits Satwant Singh, Jonathan Rose, Paul Chow, David M. Lewis
1991	J	`jnl`	A 30-b integrated logarithmic number system processor. IEEE J. Solid State Circuits Lawrence K. Yu, David M. Lewis
1991	J	`jnl`	A hierarchical compiled code event-driven logic simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David M. Lewis
1991	J	`jnl`	Hector: A Hierarchically Structured Shared-memory Multiprocessor. Computer Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White
1990	J	`jnl`	An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. IEEE Trans. Computers David M. Lewis
1990	J	`jnl`	Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. IEEE J. Solid State Circuits Jonathan Rose, Robert J. Francis, David M. Lewis, Paul Chow
1990	J	`jnl`	Device model approximation using 2 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David M. Lewis
1990	A	`conf`	Using Deducibility in Secure Network Modelling. ESORICS Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis
1989	C	`conf`	Algorithm design for a 30-bit integrated logarithmic processor. IEEE Symposium on Computer Arithmetic David M. Lewis, Lawrence K. Yu
1989	A	`conf`	Hierarchical compiled event-driven logic simulation. ICCAD David M. Lewis
1988	A*	`conf`	A Programmable Hardware Accelerator for Compiled Electrical Simulation. DAC David M. Lewis
1988	J	`jnl`	Hardware accelerators for timing simulation of VLSI digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David M. Lewis
1988	J	`jnl`	Transforming bit-serial communication circuits into fast parallel VLSI implementations. IEEE J. Solid State Circuits David M. Lewis, Brian W. Thomson, Peter I. P. Boulton, E. Stewart Lee
1986	A	`conf`	Swamp: A Fast Processor for Smalltalk-80. OOPSLA David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson
1985	A*	`conf`	A hardware engine for analogue mode simulation of MOS digital circuits. DAC David M. Lewis