David M. Bull

21 papers A* 3A 2B 1C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2019 B conf
GeST: An Automatic Framework For Generating CPU Stress-Tests.
ISPASS
Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides
2017 J jnl
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor.
IEEE J. Solid State Circuits
Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
2015 — conf
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster.
ISSCC
Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
2015 — conf
A 0.6V all-digital body-coupled wakeup transceiver for IoT applications.
VLSIC
Paul N. Whatmough, George Smart, Shidhartha Das, Yiannis Andreopoulos, David M. Bull
2015 A conf
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation.
ISLPED
Paul N. Whatmough, Shidhartha Das, David M. Bull
2015 A conf
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS.
ISLPED
Shidhartha Das, Paul N. Whatmough, David M. Bull
2014 J jnl
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull
2014 J jnl
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS.
IEEE J. Solid State Circuits
Paul N. Whatmough, Shidhartha Das, David M. Bull
2013 — conf
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation.
CICC
Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull
2013 — conf
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS.
ISSCC
Paul N. Whatmough, Shidhartha Das, David M. Bull
2013 J jnl
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms.
IEEE Trans. Very Large Scale Integr. Syst.
Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2012 — conf
Selective time borrowing for DSP pipelines with hybrid voltage control loop.
ASP-DAC
Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2011 J jnl
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
IEEE J. Solid State Circuits
David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
2011 J jnl
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
IEEE J. Solid State Circuits
David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
2011 A* conf
Error-resilient low-power DSP via path-delay shaping.
DAC
Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2010 — conf
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
ISSCC
David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
2010 C conf
A robust FIR filter with in situ error detection.
ISCAS
Paul N. Whatmough, Izzat Darwazeh, David M. Bull, Shidhartha Das, Danny Kershaw
2009 A* conf
Addressing design margins through error-tolerant circuits.
DAC
Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken
2009 J jnl
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance.
IEEE J. Solid State Circuits
Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw
2008 A* conf
DVFS in loop accelerators using BLADES.
DAC
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull
2008 — conf
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance.
ISSCC
David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull