David L. Landis

28 papers A 5B 1C 4Misc 1Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2012 A conf
Hazard driven test generation for SMT processors.
DATE
Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis
2012 J jnl
Targeted random test generation for power-aware multicore designs.
ACM Trans. Design Autom. Electr. Syst.
Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis
2010 — conf
Test Generation for CMP Designs.
MTV
Padmaraj Singh, David L. Landis
2009 — conf
Test Generation for Precise Interrupts on Out-of-Order Microprocessors.
MTV
Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan
2003 — conf
Microelectronics Education As Workforce Development.
MSE
David L. Landis, James T. Cain
2003 — conf
Short Courses in System-on-a-Chip (SoC) Design.
MSE
Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis
2003 — conf
The Sandbox Design Experience Course.
MSE
Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis
2000 J jnl
Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Bassam Shaer, David L. Landis, Sami A. Al-Arian
2000 J jnl
Partitioning sequential circuits for pseudoexhaustive testing.
IEEE Trans. Very Large Scale Integr. Syst.
Bassam Shaer, Sami A. Al-Arian, David L. Landis
1999 C conf
A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems.
IEEE International Workshop on Rapid System Prototyping
Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian
1999 — conf
Computing in Memory Architectures for Digital Image Processing.
MTDT
Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno
1999 C conf
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications.
ICCD
David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor
1999 C conf
Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use.
IEEE International Workshop on Rapid System Prototyping
David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor
1999 — conf
Pseudo-Exhaustive Testing of Sequential Circuits.
Great Lakes Symposium on VLSI
Bassam Shaer, Sami A. Al-Arian, David L. Landis
1999 — conf
Using RASSP Modules in a Rapid System Prototyping Class.
MSE
David L. Landis
1998 — conf
Partitioning algorithm to enhance VLSI testability.
ACM Southeast Regional Conference
Bassam Shaer, Sami A. Al-Arian, David L. Landis
1997 — conf
A WWW facilitated rapid system prototyping class.
MSE
David L. Landis, Paul T. Hulina
1997 — conf
An electronics manufacturing minor in engineering with emphasis on rapid prototyping.
MSE
Paul T. Hulina, David L. Landis
1996 Misc conf
A novel built-in current sensor for I
VTS
Stephan P. Athan, David L. Landis, Sami A. Al-Arian
1992 J jnl
A test methodology for wafer scale system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
David L. Landis
1992 A conf
Applications of the IEEE P1149.5 Module Test and Maintenance Bus.
ITC
David L. Landis, Chuck Hudson, Patrick F. McHugh
1992 J jnl
Wafer-Scale Optimization Using Computational Availability.
Computer
David L. Landis, Nitin Nigam, Joseph W. Yoder
1991 J jnl
Wafer Scale Integration: A university perspective.
J. VLSI Signal Process.
Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, Denny Whittaker
1990 A conf
Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration.
ITC
David L. Landis, Padmaraj Singh
1989 A conf
A Self-Test System Architecture for Reconfigurable WSI.
ITC
David L. Landis
1989 C conf
Systolic L-U decomposition array with a new reciprocal cell.
ICCD
Vijay K. Jain, David L. Landis, C. E. Alvarez
1988 A conf
Evaluation of System BIST Using Computational Performance Measures.
ITC
David L. Landis, Daniel C. Muha
1987 B conf
Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors.
ICPP
David L. Landis, Daniel C. Muha, William A. Check