David G. Chinnery

28 papers A* 4A 4C 2Journal 6Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Introduction to the Special Issue on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. Stephan Held, Gracieli Posser, Iris Hui-Ru Jiang, David G. Chinnery
2026	—	`conf`	Invited: Improving Runtime Scaling in the EDA Flow for Designs with Millions of Gates. ISPD David G. Chinnery
2023	—	`conf`	EDA for Domain Specific Computing: An Introduction for the Panel. ISPD Iris Hui-Ru Jiang, David G. Chinnery
2023	J	`jnl`	Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig
2023	—	`ed.`	Proceedings of the 2023 International Symposium on Physical Design, ISPD 2023, Virtual Event, USA, March 26-29, 2023 ISPD David G. Chinnery, Iris Hui-Ru Jiang
2023	J	`jnl`	Task-Based Parallel Programming for Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dimitrios Mangiras, David G. Chinnery, Giorgos Dimitrakopoulos
2022	—	`conf`	Integrating LR Gate Sizing in an Industrial Place-and-Route Flow. ISPD David G. Chinnery, Ankur Sharma
2021	J	`jnl`	Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos
2020	—	`conf`	Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. ISPD Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos
2020	J	`jnl`	Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankur Sharma, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu
2019	—	`conf`	Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach. ISPD Ankur Sharma, David G. Chinnery, Chris Chu
2019	—	`conf`	Session details: Detailed Routing Contest Results. ISPD David G. Chinnery
2019	J	`jnl`	Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
2017	A	`conf`	Rapid gate sizing with fewer iterations of Lagrangian Relaxation. ICCAD Ankur Sharma, David G. Chinnery, Shrirang Dhamdhere, Chris Chu
2017	A*	`conf`	Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
2015	A	`conf`	Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. ICCAD Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu
2015	—	`conf`	ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement. ISPD Ismail S. Bustany, David G. Chinnery, Joseph R. Shinnerl, Vladimir Yutsis
2014	—	`conf`	ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. ISPD Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu
2013	—	`conf`	High performance and low power design techniques for ASIC and custom in nanometer technologies. ISPD David G. Chinnery
2007	—	`book`	Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design. David G. Chinnery, Kurt Keutzer
2005	A*	`conf`	Closing the power gap between ASIC and custom: an ASIC perspective. DAC David G. Chinnery, Kurt Keutzer
2005	A	`conf`	Linear programming for sizing, V ISLPED David G. Chinnery, Kurt Keutzer
2004	—	`book`	Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design. David G. Chinnery, Kurt Keutzer
2003	C	`conf`	Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. ICCD Masayuki Ito, David G. Chinnery, Kurt Keutzer
2003	A	`conf`	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
2001	C	`conf`	A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. ICCD Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer
2001	A*	`conf`	Achieving 550Mhz in an ASIC Methodology. DAC David G. Chinnery, Borivoje Nikolic, Kurt Keutzer
2000	A*	`conf`	Closing the gap between ASIC and custom: an ASIC perspective. DAC David G. Chinnery, Kurt Keutzer