David Boland - RankMe

63 papers A* 3A 10B 6C 2Misc 3Journal 23Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification. HPCA Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi
2025	—	`conf`	Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. ASP-DAC Zijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi
2025	J	`jnl`	FPGA-based Block Minifloat Training Accelerator for a Time Series Prediction Network. ACM Trans. Reconfigurable Technol. Syst. Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong
2025	A	`conf`	Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. FPGA Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi
2025	J	`jnl`	Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuliang Guo, Binglei Lou, David Boland, Philip H. W. Leong
2025	J	`jnl`	TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification. CoRR Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi
2024	J	`jnl`	FedOrbit: Energy Efficient Federated Learning for Orbital Edge Computing Using Block Minifloat Arithmetic. IEEE Trans. Serv. Comput. Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland
2024	—	`conf`	Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration. ASPLOS (4) Ziqing Zhang, Weijie Weng, Yaning Li, Lijia Cai, Haoyu Wang, David Boland, Yungang Bao, Kan Shi
2024	B	`conf`	PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. FPL Binglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong
2024	J	`jnl`	PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. CoRR Binglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong
2024	J	`jnl`	S$^{3}$CA: A Sparse Strip Spectral Correlation Analyzer. IEEE Signal Process. Lett. Carol Jingyi Li, Richard Rademacher, David Boland, Craig T. Jin, Chad M. Spooner, Philip H. W. Leong
2024	J	`jnl`	fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library. CoRR Binglei Lou, David Boland, Philip H. W. Leong
2023	J	`jnl`	A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. ACM Trans. Reconfigurable Technol. Syst. Xiangwei Li, Douglas L. Maskell, Carol Jingyi Li, Philip H. W. Leong, David Boland
2023	A	`conf`	BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning. ICCAD Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo
2023	A	`conf`	ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. FPGA Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao
2023	J	`jnl`	Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis. ACM Trans. Reconfigurable Technol. Syst. Carol Jingyi Li, Xiangwei Li, Binglei Lou, Craig T. Jin, David Boland, Philip H. W. Leong
2023	B	`conf`	On-Board Federated Learning in Orbital Edge Computing. ICPADS Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler
2023	Misc	`conf`	Performance Analysis of Federated Learning in Orbital Edge Computing. UCC Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler
2023	A	`conf`	Single-Batch CNN Training using Block Minifloats on FPGAs. FPGA Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong
2023	J	`jnl`	fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library. ACM Trans. Reconfigurable Technol. Syst. Binglei Lou, David Boland, Philip H. W. Leong
2022	—	`conf`	FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic. APCCAS Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong
2022	J	`jnl`	Rethinking Embedded Blocks for Machine Learning Applications. ACM Trans. Reconfigurable Technol. Syst. Seyedramin Rasoulinezhad, Esther Roorda, Steve Wilton, Philip H. W. Leong, David Boland
2021	A*	`conf`	A Block Minifloat Representation for Training Deep Neural Networks. ICLR Sean Fox, Seyedramin Rasoulinezhad, Julian Faraone, David Boland, Philip H. W. Leong
2021	A	`conf`	MLBlocks: FPGA Blocks for Machine Learning Applications. FPGA Seyedramin Rasoulinezhad, David Boland, Philip H. W. Leong
2020	J	`jnl`	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
2020	J	`jnl`	Derivation of Respiratory Metrics in Health and Asthma. Sensors Joseph Prinable, Peter Jones, David Boland, Alistair Lee McEwan, Cindy Thamrin
2020	A	`conf`	LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. FPGA Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2020	J	`jnl`	LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. CoRR Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2020	J	`jnl`	MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. CoRR Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2020	—	`conf`	Real-time Automatic Modulation Classification using RFSoC. IPDPS Workshops Stephen Tridgell, David Boland, Philip H. W. Leong, Ryan Kastner, Alireza Khodamoradi, Siddhartha
2019	J	`jnl`	A Two-Speed, Radix-4, Serial-Parallel Multiplier. IEEE Trans. Very Large Scale Integr. Syst. Duncan J. M. Moss, David Boland, Philip H. W. Leong
2019	J	`jnl`	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
2019	—	`conf`	MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. FPT Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
2019	—	`conf`	Real-Time Automatic Modulation Classification. FPT Stephen Tridgell, David Boland, Philip H. W. Leong, Siddhartha
2019	—	`conf`	Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. FPT Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong
2019	J	`jnl`	Unrolling Ternary Neural Networks. CoRR Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
2019	J	`jnl`	Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
2018	B	`conf`	Customizing Low-Precision Deep Neural Networks for FPGAs. FPL Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland
2018	A	`conf`	FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. FPGA Sean Fox, David Boland, Philip Heng Wai Leong
2018	—	`conf`	Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation. MILCOM Siddhartha, Yee Hui Lee, Duncan J. M. Moss, Julian Faraone, Perry Blackmore, Daniel Salmond, David Boland, Philip H. W. Leong
2018	C	`conf`	Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. ISCAS Duncan J. M. Moss, David Boland, Peyam Pourbeik, Philip Heng Wai Leong
2018	—	`conf`	Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. FPT Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong
2017	B	`conf`	Dynamic bitwidth assignment for efficient dot products. FPL Simon Joel Schmidt, David Boland
2017	B	`conf`	FPGA acceleration of multilevel ORB feature extraction for computer vision. FPL Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond
2017	—	`conf`	FPGA-based layered/enhanced ACO-OFDM transmitter. OFC Qibing Wang, Binhuang Song, Bill Corcoran, David Boland, Leimeng Zhuang, Yiwei Xie, Arthur James Lowery
2016	A	`conf`	Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. FPGA David Boland
2015	J	`jnl`	Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. Kan Shi, David Boland, George A. Constantinides
2014	A*	`conf`	Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides
2014	—	`conf`	Efficient FPGA implementation of digit parallel online arithmetic operators. FPT Kan Shi, David Boland, George A. Constantinides
2013	J	`jnl`	A Scalable Precision Analysis Framework. IEEE Trans. Multim. David Boland, George A. Constantinides
2013	Misc	`conf`	Accuracy-Performance Tradeoffs on an FPGA through Overclocking. FCCM Kan Shi, David Boland, George A. Constantinides
2013	C	`conf`	Overclocking datapath for latency-error tradeoff. ISCAS Kan Shi, David Boland, George A. Constantinides
2013	—	`conf`	Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. FPT David Boland, George A. Constantinides
2013	A	`conf`	Word-length optimization beyond straight line code. FPGA David Boland, George A. Constantinides
2012	A	`conf`	A scalable approach for automated precision analysis. FPGA David Boland, George A. Constantinides
2012	—	`conf`	FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. ARC Xuan You Tan, David Boland, George A. Constantinides
2012	—	`—`	Precision analysis for hardware acceleration of numerical algorithms. David Boland
2011	J	`jnl`	Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Boland, George A. Constantinides
2011	J	`jnl`	Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. ACM Trans. Reconfigurable Technol. Syst. David Boland, George A. Constantinides
2011	—	`conf`	The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. ARC Christophe Le Lann, David Boland, George A. Constantinides
2010	Misc	`conf`	Automated Precision Analysis: A Polynomial Algebraic Approach. FCCM David Boland, George A. Constantinides
2010	—	`conf`	Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. ARC David Boland, George A. Constantinides
2008	B	`conf`	An FPGA-based implementation of the MINRES algorithm. FPL David Boland, George A. Constantinides