David Bol - RankMe

127 papers A 7B 1C 12Misc 1Journal 65Unranked 40

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	A Power Consumption Model for Customer Premise Equipment: Methodology and Application. SoftCOM Robin Dethienne, Jérôme Louveaux, David Bol
2025	J	`jnl`	A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11- μ m Bulk and 22-nm FD-SOI. IEEE J. Solid State Circuits Martin Lefebvre, David Bol
2025	—	`conf`	Exploring the Direct and Indirect Environmental Impacts of Mobile Health - A Case Study on Continuous Glucose Monitoring. ICT4S Augustin Wattiez, Rémi Dekimpe, Thibault Pirson, David Bol
2025	J	`jnl`	IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping. IEEE Trans. Circuits Syst. Artif. Intell. Adrian Kneip, Martin Lefebvre, Pol Maistriaux, David Bol
2025	J	`jnl`	MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. IEEE J. Solid State Circuits Martin Lefebvre, David Bol
2025	J	`jnl`	Purer than pure: how purity reshapes the upstream materiality of the semiconductor industry. CoRR Gauthier Roussilhe, Thibault Pirson, David Bol, Srinjoy Mitra
2024	J	`jnl`	A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11- μ m Bulk and 22-nm FD-SOI. IEEE J. Solid State Circuits Martin Lefebvre, David Bol
2024	J	`jnl`	A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-μm Bulk and 22-nm FD-SOI. CoRR Martin Lefebvre, David Bol
2024	J	`jnl`	A Combined Analytical and Simulation-Based Methodology for Quantifying the Noise-Power-Area Trade-Offs in Biomedical Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Sylvain Favresse, David Bol, Denis Flandre
2024	J	`jnl`	A Cradle-to-Gate Life Cycle Analysis of Bitcoin Mining Equipment Using Sphera LCA and ecoinvent Databases. CoRR Ludmila Courtillat-Piazza, Thibault Pirson, Louis Golard, David Bol
2024	—	`conf`	A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. CICC Martin Lefebvre, David Bol
2024	C	`conf`	A Narrowband RF Front End in 22-nm FD-SOI Featuring a Programmable Low-Noise Amplifier with a Configurable Noise-Power Trade-Off. ISCAS Marco Gonzalez, Pol Maistriaux, David Bol
2024	B	`conf`	A Parametric Power Model of Multi-Band Sub-6 GHz Cellular Base Stations Using On-Site Measurements. PIMRC Louis Golard, Youssef Agram, François Rottenberg, François Quitin, David Bol, Jérôme Louveaux
2024	J	`jnl`	A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-μm Bulk and 22-nm FD-SOI. CoRR Martin Lefebvre, David Bol
2024	J	`jnl`	Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rémi Dekimpe, David Bol
2024	J	`jnl`	IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping. CoRR Adrian Kneip, Martin Lefebvre, Pol Maistriaux, David Bol
2024	—	`conf`	Leveraging a Digital Chirp Spread Spectrum Detector for LPWAN Wake-Up Receivers. CSNDSP Pol Maistriaux, Marco Gonzalez, Jérôme Louveaux, David Bol
2024	J	`jnl`	MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. CoRR Martin Lefebvre, David Bol
2023	J	`jnl`	A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. CoRR Martin Lefebvre, Denis Flandre, David Bol
2023	J	`jnl`	A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. IEEE J. Solid State Circuits Martin Lefebvre, Denis Flandre, David Bol
2023	J	`jnl`	A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias. IEEE Trans. Circuits Syst. I Regul. Pap. Adrian Kneip, David Bol
2023	J	`jnl`	A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios. IEEE Open J. Circuits Syst. Mathieu Xhonneux, Jérôme Louveaux, David Bol
2023	J	`jnl`	Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing. IEEE Trans. Circuits Syst. II Express Briefs Pengcheng Xu, Denis Flandre, David Bol
2023	J	`jnl`	Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence. Proc. IEEE Charlotte Frenkel, David Bol, Giacomo Indiveri
2023	J	`jnl`	Evaluation and projection of 4G and 5G RAN energy footprints: the case of Belgium for 2020-2025. Ann. des Télécommunications Louis Golard, Jérôme Louveaux, David Bol
2023	J	`jnl`	IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm IEEE J. Solid State Circuits Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
2023	A	`conf`	Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW. DATE Marco Gonzalez, David Bol
2023	J	`jnl`	Technical and Ecological Limits of 2.45-GHz Wireless Power Transfer for Battery-Less Sensors. IEEE Internet Things J. Marco Gonzalez, Pengcheng Xu, Rémi Dekimpe, Maxime Schramme, Ivan Stupia, Thibault Pirson, David Bol
2023	J	`jnl`	UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI. IEEE Trans. Circuits Syst. I Regul. Pap. Maxime Schramme, David Bol
2022	—	`conf`	A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI. ESSCIRC Martin Lefebvre, Denis Flandre, David Bol
2022	—	`conf`	A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization. ESSCIRC Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
2022	J	`jnl`	A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs. IEEE Trans. Circuits Syst. I Regul. Pap. Martin Lefebvre, David Bol
2022	J	`jnl`	A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm with 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs. CoRR Martin Lefebvre, David Bol
2022	J	`jnl`	A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets. IEEE Internet Things J. Mathieu Xhonneux, Orion Afisiadis, David Bol, Jérôme Louveaux
2022	J	`jnl`	Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate. IEEE Trans. Circuits Syst. I Regul. Pap. Léopold Van Brandt, Roghayeh Saeidi, David Bol, Denis Flandre
2022	J	`jnl`	Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control. IEEE Trans. Circuits Syst. I Regul. Pap. Maxime Schramme, Léopold Van Brandt, Denis Flandre, David Bol
2022	J	`jnl`	ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller. IEEE Trans. Biomed. Circuits Syst. Rémi Dekimpe, David Bol
2022	J	`jnl`	From Silicon Shield to Carbon Lock-in ? The Environmental Footprint of Electronic Components Manufacturing in Taiwan (2015-2020). CoRR Gauthier Roussilhe, Thibault Pirson, Mathieu Xhonneux, David Bol
2022	—	`conf`	Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End. ESSCIRC Rémi Dekimpe, David Bol
2022	—	`conf`	Modeling the Carbon Footprint of Battery-Powered IoT Sensor Nodes for Environmental-Monitoring Applications. IOT Pol Maistriaux, Thibault Pirson, Maxime Schramme, Jérôme Louveaux, David Bol
2022	—	`conf`	The Environmental Footprint of IC Production: Meta-Analysis and Historical Trends. ESSDERC Thibault Pirson, Thibault P. Delhaye, Alex Pip, Grégoire Le Brun, Jean-Pierre Raskin, David Bol
2021	—	`conf`	A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. ISSCC Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol
2021	J	`jnl`	A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Rémi Dekimpe, David Bol
2021	J	`jnl`	A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform. IEEE J. Solid State Circuits Pengcheng Xu, Denis Flandre, David Bol
2021	—	`conf`	A Two-User Successive Interference Cancellation LoRa Receiver with Soft-Decoding. ACSCC Mathieu Xhonneux, Joachim Tapparel, Péter Scheepers, Orion Afisiadis, Alexios Balatsoukas-Stimming, David Bol, Jérôme Louveaux, Andreas Burg
2021	J	`jnl`	Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach. CoRR Thibault Pirson, David Bol
2021	J	`jnl`	Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence. CoRR Charlotte Frenkel, David Bol, Giacomo Indiveri
2021	J	`jnl`	Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers. IEEE Open J. Commun. Soc. Joachim Tapparel, Mathieu Xhonneux, David Bol, Jérôme Louveaux, Andreas Burg
2021	J	`jnl`	Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Adrian Kneip, David Bol
2021	—	`conf`	Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller. SiPS Mathieu Xhonneux, Jérôme Louveaux, David Bol
2021	A	`conf`	Moore's Law and ICT Innovation in the Anthropocene. DATE David Bol, Thibault Pirson, Rémi Dekimpe
2021	—	`conf`	SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham
2021	—	`conf`	SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol
2021	J	`jnl`	SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre
2020	C	`conf`	A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. ISCAS Charlotte Frenkel, Jean-Didier Legat, David Bol
2020	J	`jnl`	A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. CoRR Charlotte Frenkel, Jean-Didier Legat, David Bol
2020	J	`jnl`	Ask Less, Get More: Side-Channel Signal Hiding, Revisited. IEEE Trans. Circuits Syst. Itamar Levi, Davide Bellizia, David Bol, François-Xavier Standaert
2019	J	`jnl`	A 0.086-mm IEEE Trans. Biomed. Circuits Syst. Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, David Bol
2019	C	`conf`	A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ISCAS Ludovic Moreau, Rémi Dekimpe, David Bol
2019	—	`conf`	A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. ISSCC David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre
2019	C	`conf`	A 65-nm 738k-Synapse/mm ISCAS Charlotte Frenkel, Jean-Didier Legat, David Bol
2019	J	`jnl`	A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer. Integr. Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Pierre Gérard, Denis Flandre, David Bol
2019	J	`jnl`	Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors. IEEE J. Solid State Circuits Pengcheng Xu, Denis Flandre, David Bol
2019	J	`jnl`	Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training. CoRR Charlotte Frenkel, Martin Lefebvre, David Bol
2019	J	`jnl`	MorphIC: A 65-nm 738k-Synapse/mm CoRR Charlotte Frenkel, Jean-Didier Legat, David Bol
2019	J	`jnl`	MorphIC: A 65-nm 738k-Synapse/mm IEEE Trans. Biomed. Circuits Syst. Charlotte Frenkel, Jean-Didier Legat, David Bol
2018	J	`jnl`	A 0.086-mm CoRR Charlotte Frenkel, Jean-Didier Legat, David Bol
2018	J	`jnl`	A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. François Stas, David Bol
2018	—	`conf`	A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. PATMOS Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Denis Flandre, David Bol
2018	J	`jnl`	A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks. IEEE Trans. Ind. Electron. Javier Aguirre, David Bol, Denis Flandre, Carlos Sánchez-Azqueta, Santiago Celma
2018	J	`jnl`	Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis. IEEE Trans. Circuits Syst. I Regul. Pap. Cecilia Gimeno, Denis Flandre, David Bol
2018	—	`conf`	Demonstrating an LPPN Processor. ASHES@CCS Dina Kamel, Davide Bellizia, François-Xavier Standaert, Denis Flandre, David Bol
2018	—	`conf`	Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. A-SSCC Pengcheng Xu, Denis Flandre, David Bol
2018	A	`conf`	Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. DATE Thomas Haine, Johan Segers, Denis Flandre, David Bol
2018	—	`conf`	Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI. LASCAS Cecilia Gimeno, Denis Flandre, David Bol
2018	J	`jnl`	Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits. IEEE Trans. Very Large Scale Integr. Syst. Cecilia Gimeno, David Bol, Denis Flandre
2017	C	`conf`	A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS. ISCAS François Stas, David Bol
2017	—	`conf`	A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors. BioCAS Charlotte Frenkel, Jean-Didier Legat, David Bol
2017	C	`conf`	A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. ISCAS Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol
2017	—	`conf`	An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. ESSCIRC Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol
2017	—	`conf`	Architecture exploration of a fixed point computation unit using precise timing spiking neurons. PATMOS Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
2017	C	`conf`	Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. ISCAS François Stas, David Bol
2017	J	`jnl`	SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. IEEE J. Solid State Circuits Guerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, Andreia Cathelin, David Bol
2016	—	`conf`	CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. ICDSC Thomas Haine, François Stas, Guerric de Streel, Cecilia Gimeno, Denis Flandre, David Bol
2016	C	`conf`	Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. VLSI-SoC Charlotte Frenkel, Jean-Didier Legat, David Bol
2016	—	`conf`	Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools. NEWCAS François Stas, Guerric de Streel, David Bol
2016	—	`conf`	SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape. VLSI Circuits Guerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, David Bol
2016	—	`conf`	Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers. SPACE Dina Kamel, Guerric de Streel, Santos Merino Del Pozo, Kashif Nawaz, François-Xavier Standaert, Denis Flandre, David Bol
2016	J	`jnl`	Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol
2015	—	`conf`	8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester
2015	—	`conf`	A 0.48mm ESSCIRC David Bol, El Hafed Boufouss, Denis Flandre, Julien De Vos
2015	J	`jnl`	A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. IEEE J. Solid State Circuits Numa Couniot, Guerric de Streel, François Botman, Angelo Kuti Lusala, Denis Flandre, David Bol
2015	J	`jnl`	A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz. IEEE Trans. Circuits Syst. II Express Briefs Numa Couniot, David Bol, Olivier Poncelet, Laurent A. Francis, Denis Flandre
2015	—	`conf`	A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. ReCoSoC Charlotte Frenkel, Jean-Didier Legat, David Bol
2015	C	`conf`	Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. ISCAS Ahmed T. Elthakeb, Thomas Haine, Denis Flandre, Yehea Ismail, Hamdy Abd Elhamid, David Bol
2014	—	`conf`	A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range. VLSIC David Bol, Guerric de Streel, François Botman, Angelo Kuti Lusala, Numa Couniot
2014	J	`jnl`	A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks. IEEE Trans. Emerg. Top. Comput. Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren
2014	J	`jnl`	A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville
2014	J	`jnl`	A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Julien De Vos, Denis Flandre, David Bol
2014	C	`conf`	Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. ISCAS François Botman, Julien De Vos, Sebastien Bernard, François Stas, Jean-Didier Legat, David Bol
2014	J	`jnl`	Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. François Botman, David Bol, Jean-Didier Legat, Kaushik Roy
2014	—	`conf`	Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol
2013	—	`conf`	An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat
2013	A	`conf`	Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology. ISLPED Guerric de Streel, David Bol
2013	J	`jnl`	SleepWalker: A 25-MHz 0.4-V Sub-mm IEEE J. Solid State Circuits David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat
2012	—	`conf`	A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. ISSCC David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat
2012	J	`jnl`	A Fast ULV Logic Synthesis Flow in Many-V IEEE Trans. Circuits Syst. II Express Briefs David Bol, Cédric Hocquet, Francesco Regazzoni
2012	J	`jnl`	Pushing Adaptive Voltage Scaling Fully on Chip. J. Low Power Electron. Julien De Vos, Denis Flandre, David Bol
2012	A	`conf`	Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint. CHES Stéphanie Kerckhof, François Durvaux, Cédric Hocquet, David Bol, François-Xavier Standaert
2011	—	`conf`	Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation. RFIDSec Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren
2011	J	`jnl`	Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. J. Cryptogr. Eng. Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert
2010	—	`conf`	Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits. ESSCIRC Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol
2010	J	`jnl`	Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. ACM Trans. Design Autom. Electr. Syst. David Bol, Denis Flandre, Jean-Didier Legat
2010	C	`conf`	Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. ISCAS David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat
2010	—	`conf`	The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. ESSCIRC David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat
2009	J	`jnl`	Interests and Limitations of Technology Scaling for Subthreshold Logic. IEEE Trans. Very Large Scale Integr. Syst. David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2009	A	`conf`	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ISLPED David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat
2009	A	`conf`	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. ISLPED David Bol, Denis Flandre, Jean-Didier Legat
2008	C	`conf`	Analysis and minimization of practical energy in 45nm subthreshold logic circuits. ICCD David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2008	—	`conf`	Impact of Technology Scaling on Digital Subthreshold Circuits. ISVLSI David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2008	—	`—`	Pushing ultra-low-power digital circuits into the nanometer era. David Bol
2007	—	`conf`	Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices. ICECS David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2007	J	`jnl`	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. J. Multiple Valued Log. Soft Comput. David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat
2006	J	`jnl`	Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. J. Low Power Electron. Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, Jean-Didier Legat
2006	—	`conf`	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. ASAP Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat
2006	—	`conf`	Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo
2005	—	`conf`	Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. PATMOS Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat