David Biancolin

14 papers A* 2A 4B 1C 1Journal 4Unranked 1

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Simulator Independent Coverage for RTL Hardware Languages. ASPLOS (3) Kevin Laeufer, Vighnesh Iyer, David Biancolin, Jonathan Bachrach, Borivoje Nikolic, Koushik Sen
2021	J	`jnl`	Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim. IEEE Micro David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolic, Jonathan Bachrach, Krste Asanovic
2021	—	`—`	Automated, FPGA-Based Hardware Emulation of Dynamic Frequency Scaling David Biancolin
2020	J	`jnl`	Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. IEEE Micro Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic
2020	A*	`conf`	Invited: Chipyard - An Integrated SoC Research and Implementation Environment. DAC Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Jonathan Bachrach, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic
2019	A	`conf`	FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. FPGA David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic
2019	J	`jnl`	FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. IEEE Micro Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Howard Katz, Jonathan Bachrach, Krste Asanovic
2019	A	`conf`	Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes. ICCAD Albert Magyar, David Biancolin, John Koenig, Sanjit A. Seshia, Jonathan Bachrach, Krste Asanovic
2018	B	`conf`	DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles. FPL Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanovic
2018	A*	`conf`	FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. ISCA Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy H. Katz, Jonathan Bachrach, Krste Asanovic
2017	C	`conf`	A Hardware Accelerator for Computing an Exact Dot Product. ARITH Jack Koenig, David Biancolin, Jonathan Bachrach, Krste Asanovic
2016	J	`jnl`	Fine-Grained Interconnect Synthesis. ACM Trans. Reconfigurable Technol. Syst. Alex Rodionov, David Biancolin, Jonathan Rose
2016	A	`conf`	JITPCB. IROS Jonathan Bachrach, David Biancolin, Austin Buchan, Duncan W. Haldane, Richard Lin
2015	A	`conf`	Fine-Grained Interconnect Synthesis. FPGA Alex Rodionov, David Biancolin, Jonathan Rose