David B. Thomas

118 papers A* 1A 5B 23C 3Misc 16Journal 32Unranked 37

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Quantitative simulations of Spiking Neural Networks on an event-driven FPGA cluster. Integr. Zilong Liang, Xinbo Zhang, Mark Vousden, David B. Thomas, Graeme M. Bragg
2025	—	`conf`	LatentGraph: From Latent States to Rule-based Expressions for Explainable Financial Forecasting. ICAIF Ekin Can Erkus, Alex Chan, Walter Distaso, David B. Thomas, Alex Yakovlev, Rishad A. Shafik
2024	J	`jnl`	An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster. IEEE ACM Trans. Comput. Biol. Bioinform. Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark L. Vousden, David B. Thomas, Alex Yakovlev, Andrew D. Brown
2023	J	`jnl`	Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems. Array Mahyar Shahsavari, David B. Thomas, Marcel van Gerven, Andrew D. Brown, Wayne Luk
2023	J	`jnl`	An Event-Driven Approach To Genotype Imputation On A Custom RISC-V FPGA Cluster. CoRR Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark Vousden, David B. Thomas, Alex Yakovlev, Andrew Brown
2023	J	`jnl`	Event-based high throughput computing: A series of case studies on a massively parallel softcore machine. IET Comput. Digit. Tech. Mark Vousden, Jordan Morris, Graeme McLachlan Bragg, Jonathan Beaumont, Ashur Rafiev, Wayne Luk, David B. Thomas, Andrew D. Brown
2023	J	`jnl`	POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
2022	—	`conf`	Non-deterministic event brokered computing. HEART Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev
2022	J	`jnl`	Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown
2022	J	`jnl`	Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown
2021	C	`conf`	General hardware multicasting for fine-grained message-passing architectures. PDP Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2021	—	`conf`	Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture. ICONS Mahyar Shahsavari, David B. Thomas, Andrew D. Brown, Wayne Luk
2020	B	`conf`	A Hardware/Application Overlay Model for Large-Scale Neuromorphic Simulation. IJCNN Alexander Rast, Mahyar Shahsavari, Graeme M. Bragg, Mark Vousden, David B. Thomas, Andrew D. Brown
2020	—	`conf`	Exploring performance enhancement of event-driven processor networks. FPT Tim Todman, David B. Thomas, Wayne Luk
2020	—	`conf`	Termination detection for fine-grained message-passing architectures. ASAP Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2019	B	`conf`	Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
2019	C	`conf`	Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools. ARITH David B. Thomas
2019	Misc	`conf`	Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. FCCM Florian Faissole, George A. Constantinides, David B. Thomas
2019	—	`conf`	POETS: Distributed Event-Based Computing - Scaling Behaviour. PARCO Andrew D. Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov
2019	Misc	`conf`	Templatised Soft Floating-Point for High-Level Synthesis. FCCM David B. Thomas
2019	B	`conf`	Tinsel: A Manythread Overlay for FPGA Clusters. FPL Matthew Naylor, Simon W. Moore, David B. Thomas
2018	J	`jnl`	A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers. IEEE Trans. Very Large Scale Integr. Syst. Aryan Tavakkoli, David B. Thomas
2018	—	`conf`	Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
2018	—	`conf`	Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
2018	J	`jnl`	Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
2018	—	`conf`	Injecting FPGA Configuration Faults in Parallel. FPT Shane T. Fleming, David B. Thomas
2018	—	`conf`	Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
2017	J	`jnl`	A Domain Specific Approach to High Performance Heterogeneous Computing. IEEE Trans. Parallel Distributed Syst. Gordon Inggs, David B. Thomas, Wayne Luk
2017	—	`conf`	Distributed Event-Based Computing. PARCO Andrew D. Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski
2017	—	`conf`	Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew D. Brown
2017	Misc	`conf`	Using Runahead Execution to Hide Memory Latency in High Level Synthesis. FCCM Shane T. Fleming, David B. Thomas
2016	—	`conf`	AT-GIS: Highly Parallel Spatial Query Processing with Associative Transducers. SIGMOD Conference Peter Ogden, David B. Thomas, Peter R. Pietzuch
2016	Misc	`conf`	Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM Jiang Su, David B. Thomas, Peter Y. K. Cheung
2016	J	`jnl`	Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung
2016	A*	`conf`	StitchUp: automatic control flow protection for high level synthesis circuits. DAC Shane T. Fleming, David B. Thomas
2016	Misc	`conf`	SynADT: Dynamic Data Structures in High Level Synthesis. FCCM Zeping Xue, David B. Thomas
2016	—	`conf`	Synthesisable recursion for C++ HLS tools. ASAP David B. Thomas
2015	C	`conf`	A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs. ARITH David B. Thomas
2015	J	`jnl`	A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms. J. Inf. Process. Takaaki Miyajima, David B. Thomas, Hideharu Amano
2015	J	`jnl`	A general-purpose framework for FPGA-accelerated genetic algorithms. Int. J. Bio Inspired Comput. Liucheng Guo, Andreea-Ingrid Funie, Zhongliu Xie, David B. Thomas, Wayne Luk
2015	J	`jnl`	An Efficient, Automatic Approach to High Performance Heterogeneous Computing. CoRR Gordon Inggs, David B. Thomas, Wayne Luk
2015	J	`jnl`	Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. IPSJ Trans. Syst. LSI Des. Methodol. Takaaki Miyajima, David B. Thomas, Hideharu Amano
2015	J	`jnl`	Parallel Genetic Algorithms on Multiple FPGAs. SIGARCH Comput. Archit. News Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk
2015	Misc	`conf`	Pipelined Genetic Propagation. FCCM Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk
2015	B	`conf`	PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica
2015	B	`conf`	Recursive pipelined genetic propagation for bilevel optimisation. FPL Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston
2015	J	`jnl`	Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR Gordon Inggs, David B. Thomas, George A. Constantinides, Wayne Luk
2015	B	`conf`	SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems. FPL Zeping Xue, David B. Thomas
2015	A	`conf`	System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica
2015	J	`jnl`	The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator. ACM Trans. Reconfigurable Technol. Syst. David B. Thomas
2015	A	`conf`	Transparent linking of compiled software and synthesized hardware. DATE David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica
2014	J	`jnl`	A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility. CoRR Gordon Inggs, David B. Thomas, Wayne Luk
2014	J	`jnl`	An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms. CoRR Takaaki Miyajima, David B. Thomas, Hideharu Amano
2014	B	`conf`	Area implications of memory partitioning for high-level synthesis on FPGAs. FPL Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides
2014	B	`conf`	Automated Framework for General-Purpose Genetic Algorithms in FPGAs. EvoApplications Liucheng Guo, David B. Thomas, Wayne Luk
2014	B	`conf`	Automated framework for FPGA-based parallel genetic algorithms. FPL Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk
2014	Misc	`conf`	Compiling Higher Order Functional Programs to Composable Digital Hardware. FCCM Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides
2014	Misc	`conf`	FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy. FCCM David B. Thomas
2014	B	`conf`	Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. FPL Shane T. Fleming, David B. Thomas
2014	—	`conf`	Is high level synthesis ready for business? A computational finance case study. FPT Gordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk
2014	—	`conf`	Low-latency option pricing using systolic binomial trees. FPT Aryan Tavakkoli, David B. Thomas
2013	B	`conf`	A Heterogeneous Computing Framework for Computational Finance. ICPP Gordon Inggs, David B. Thomas, Wayne Luk
2013	B	`conf`	A fully pipelined FPGA architecture for stochastic simulation of chemical systems. FPL David B. Thomas, Hideharu Amano
2013	J	`jnl`	Customisable architectures for the set covering problem. SIGARCH Comput. Archit. News Liucheng Guo, David B. Thomas, Wayne Luk
2013	B	`conf`	FPGA based control for real time systems. FPL Shane T. Fleming, David B. Thomas
2013	—	`conf`	Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields. ARC Shane T. Fleming, David B. Thomas
2013	J	`jnl`	Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. David B. Thomas, Wayne Luk
2013	Misc	`conf`	Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform. FCCM David B. Thomas
2013	J	`jnl`	Scalable XML Query Processing using Parallel Pushdown Transducers. Proc. VLDB Endow. Peter Ogden, David B. Thomas, Peter R. Pietzuch
2013	J	`jnl`	The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. David B. Thomas, Wayne Luk
2012	Misc	`conf`	A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU. ICNC Takaaki Miyajima, David B. Thomas, Hideharu Amano
2012	—	`conf`	A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. ASAP Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
2012	A	`conf`	A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. FPGA Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas
2012	J	`jnl`	Design Exploration of Quadrature Methods in Option Pricing. IEEE Trans. Very Large Scale Integr. Syst. Anson H. T. Tse, David B. Thomas, Wayne Luk
2012	B	`conf`	Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA. FPL Gordon Inggs, David B. Thomas, Simon Winberg
2012	—	`conf`	Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. ARC Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston
2012	—	`conf`	Optimising Performance of Quadrature Methods with Reduced Precision. ARC Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk
2012	B	`conf`	Optimising explicit finite difference option pricing for dynamic constant reconfiguration. FPL Qiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas
2012	B	`conf`	Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. FPL Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
2011	—	`conf`	A framework for FPGA acceleration of large graph problems: Graphlet counting case study. FPT Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj
2011	—	`—`	Management and programming of reconfigurable hardware resources. David B. Thomas
2011	Misc	`conf`	On Comparing Financial Option Price Solvers on FPGA. FCCM Qiwei Jin, Wayne Luk, David B. Thomas
2011	B	`conf`	Unifying Finite Difference Option-Pricing for Hardware Acceleration. FPL Qiwei Jin, Wayne Luk, David B. Thomas
2010	—	`conf`	An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. ASAP David B. Thomas, Wayne Luk
2010	—	`conf`	Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT Brahim Betkaoui, David B. Thomas, Wayne Luk
2010	—	`conf`	Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. FPT Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010	J	`jnl`	Efficient reconfigurable design for pricing asian options. SIGARCH Comput. Archit. News Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010	B	`conf`	FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. FPL David B. Thomas, Wayne Luk
2010	B	`conf`	Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. FPL Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2009	A	`conf`	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. FPGA David B. Thomas, Lee W. Howes, Wayne Luk
2009	Misc	`conf`	Accelerating Quadrature Methods for Option Valuation. FCCM Anson H. T. Tse, David B. Thomas, Wayne Luk
2009	J	`jnl`	Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. ACM Trans. Reconfigurable Technol. Syst. Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope
2009	B	`conf`	Exploring reconfigurable architectures for explicit finite difference option pricing models. FPL Qiwei Jin, David B. Thomas, Wayne Luk
2009	—	`conf`	FPGA Accelerated Low-Latency Market Data Feed Processing. Hot Interconnects Gareth W. Morris, David B. Thomas, Wayne Luk
2009	Misc	`conf`	FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. FCCM David B. Thomas, Wayne Luk
2008	—	`conf`	An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk
2008	Misc	`conf`	Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. FCCM David B. Thomas, Wayne Luk
2008	—	`conf`	Estimation of sample mean and variance for Monte-Carlo simulations. FPT David B. Thomas, Wayne Luk
2008	—	`conf`	Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope
2008	A	`conf`	FPGA-optimised high-quality uniform random number generators. FPGA David B. Thomas, Wayne Luk
2008	J	`jnl`	Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. David B. Thomas, Wayne Luk
2008	—	`conf`	Resource efficient generators for the floating-point uniform and exponential distributions. ASAP David B. Thomas, Wayne Luk
2008	B	`conf`	Sampling from the exponential distribution using independent Bernoulli variates. FPL David B. Thomas, Wayne Luk
2007	—	`conf`	A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. FPT David B. Thomas, Wayne Luk
2007	—	`conf`	Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. ASAP David B. Thomas, Jacob A. Bower, Wayne Luk
2007	J	`jnl`	Gaussian random number generators. ACM Comput. Surv. David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor
2007	J	`jnl`	High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. J. VLSI Signal Process. David B. Thomas, Wayne Luk
2007	J	`jnl`	Non-uniform random number generation through piecewise linear approximations. IET Comput. Digit. Tech. David B. Thomas, Wayne Luk
2007	—	`conf`	Reconfigurable Hardware Acceleration of Canonical Graph Labelling. ARC David B. Thomas, Wayne Luk, Michael Stumpf
2007	Misc	`conf`	Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. FCCM David B. Thomas, Wayne Luk
2006	—	`conf`	A Reconfigurable Simulation Framework for Financial Computation. ReConFig Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer
2006	Misc	`conf`	Efficient Hardware Generation of Random Variates with Arbitrary Distributions. FCCM David B. Thomas, Wayne Luk
2006	—	`conf`	Hardware architectures for Monte-Carlo based financial simulations. FPT David B. Thomas, Jacob A. Bower, Wayne Luk
2006	B	`conf`	Non-Uniform Random Number Generation Through Piecewise Linear Approximations. FPL David B. Thomas, Wayne Luk
2005	—	`conf`	High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. FPT David B. Thomas, Wayne Luk
2005	—	`conf`	High quality uniform random number generation for massively parallel simulations in FPGA. ReConFig David B. Thomas, Wayne Luk
2004	B	`conf`	Implementing Graphics Shaders Using FPGAs. FPL David B. Thomas, Wayne Luk
2004	—	`conf`	Pipelining designs with loop-carried dependencies. FPT Henry Styles, David B. Thomas, Wayne Luk