David Andrews - RankMe

80 papers A 9B 11C 1Misc 11Journal 20Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing. ACM Trans. Reconfigurable Technol. Syst. M. D. Arafat Kabir, Nathaniel Fredricks, Tendayi Kamucheka, Joel Mandebi, Miaoqing Huang, Jason D. Bakos, David Andrews
2025	Misc	`conf`	N-TORC: Native Tensor Optimizer for Real-Time Constraints. FCCM Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos
2025	J	`jnl`	N-TORC: Native Tensor Optimizer for Real-time Constraints. CoRR Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos
2025	Misc	`conf`	Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms. FCCM Ehsan Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang
2025	A	`conf`	Resource Scheduling for Real-Time Machine Learning. FPGA Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos
2024	J	`jnl`	A Runtime-Adaptive Transformer Neural Network Accelerator on FPGAs. CoRR Ehsan Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang
2024	J	`jnl`	FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs. CoRR Ehsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang
2024	—	`conf`	Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs. ICFPT Ehsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang
2024	B	`conf`	IMAGine: An In-Memory Accelerated GEMV Engine Overlay. FPL M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews
2024	J	`jnl`	IMAGine: An In-Memory Accelerated GEMV Engine Overlay. CoRR M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews
2024	Misc	`conf`	Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators. FCCM Tendayi Kamucheka, David Andrews
2024	—	`conf`	ProTEA: Programmable Transformer Encoder Acceleration on FPGA. SC Workshops Ehsan Kabir, Jason D. Bakos, David Andrews, Miaoqing Huang
2024	J	`jnl`	ProTEA: Programmable Transformer Encoder Acceleration on FPGA. CoRR Ehsan Kabir, Jason D. Bakos, David Andrews, Miaoqing Huang
2024	Misc	`conf`	The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. FCCM M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews
2024	J	`jnl`	The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. CoRR M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews
2023	B	`conf`	Accelerating LSTM-Based High-Rate Dynamic System Models. FPL Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang
2023	J	`jnl`	Accelerating LSTM-based High-Rate Dynamic System Models. CoRR Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang
2023	B	`conf`	FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? FPL M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews
2023	J	`jnl`	FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? CoRR M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews
2023	Misc	`conf`	Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays. FCCM M. D. Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews
2022	—	`conf`	A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm. FPT Tendayi Kamucheka, Alexander Nelson, David Andrews, Miaoqing Huang
2022	J	`jnl`	A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm. IACR Cryptol. ePrint Arch. Tendayi Kamucheka, Alexander Nelson, David Andrews, Miaoqing Huang
2022	—	`conf`	A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA. ARC Ehsan Kabir, Arpan Poudel, Zeyad Aklah, Miaoqing Huang, David Andrews
2022	Misc	`conf`	High-Rate Machine Learning for Forecasting Time-Series Signals. FCCM Atiyehsadat Panahi, Ehsan Kabir, Austin R. J. Downey, David Andrews, Miaoqing Huang, Jason D. Bakos
2021	B	`conf`	A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications. FPL Atiyehsadat Panahi, Suhail Basalama, Ange-Thierry Ishimwe, Joel Mandebi Mbongue, David Andrews
2021	J	`jnl`	Power-based Side Channel Attack Analysis on PQC Algorithms. IACR Cryptol. ePrint Arch. Tendayi Kamucheka, Michael Fahr, Tristen Teague, Alexander Nelson, David Andrews, Miaoqing Huang
2020	—	`conf`	An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks. FPT Haoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson
2020	Misc	`conf`	FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks. FCCM Haoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson
2020	—	`conf`	SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices. ICDIS Suhail Basalama, Atiyehsadat Panahi, Ange-Thierry Ishimwe, David Andrews
2019	—	`ed.`	2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019 ReConFig David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner
2019	—	`conf`	A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs. ReConFig Atiyehsadat Panahi, Keaten Stokke, David Andrews
2019	J	`jnl`	An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. J. Signal Process. Syst. Tim Hansmeier, Marco Platzner, Md Jubaer Hossain Pantho, David Andrews
2018	—	`ed.`	2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018 ReConFig David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt
2018	—	`conf`	An FPGA/HMC-Based Accelerator for Resolution Proof Checking. ARC Tim Hansmeier, Marco Platzner, David Andrews
2018	Misc	`conf`	Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer. FCCM Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews, Marjan Asadinia
2018	—	`conf`	FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud. IEEE CLOUD Joel Mandebi Mbongue, Festus Hategekimana, Danielle Tchuinkou Kwadjo, David Andrews, Christophe Bobda
2018	—	`conf`	Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers. FPT Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews
2016	J	`jnl`	A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators. CoRR Zeyad Aklah, Sen Ma, David Andrews
2016	—	`conf`	Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud. ReConFig Sen Ma, David Andrews, Shanyuan Gao, Jaime Cummins
2016	A	`conf`	Just In Time Assembly of Accelerators. FPGA Sen Ma, Zeyad Aklah, David Andrews
2016	—	`conf`	OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods. IPDPS Workshops Hongyuan Ding, Sen Ma, Miaoqing Huang, David Andrews
2016	—	`conf`	Programming models for reconfigurable manycore systems. ReCoSoC David Andrews, Marco Platzner
2016	A	`conf`	Run time interpretation for creating custom accelerators. DATE Sen Ma, Zeyad Aklah, David Andrews
2015	—	`conf`	A Flexible Multilayer Perceptron Co-processor for FPGAs. ARC Zeyad Aklah, David Andrews
2015	B	`conf`	A run time interpretation approach for creating custom accelerators. FPL Sen Ma, Zeyad Aklah, David Andrews
2015	—	`conf`	Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures. ReConFig Sen Ma, Hongyuan Ding, Miaoqing Huang, David Andrews
2015	B	`conf`	Automatic support for multi-module parallelism from computational patterns. FPL Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne
2014	B	`conf`	Achieving portability and efficiency over chip heterogeneous multiprocessor systems. FPL Eugene Cartwright, Alborz Sadeghian, Sen Ma, David Andrews
2014	A	`conf`	On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only). FPGA Sen Ma, David Andrews
2014	J	`jnl`	Operating Systems Research for Reconfigurable Computing. IEEE Micro David Andrews
2013	J	`jnl`	Modular Design of Fully Pipelined Reduction Circuits on FPGAs. IEEE Trans. Parallel Distributed Syst. Miaoqing Huang, David Andrews
2012	B	`conf`	Automating the design of mLUT MPSoPC FPGAs in the cloud. FPL Eugene Cartwright, Azad Fahkari, Sen Ma, Christina Smith, Miaoqing Huang, David Andrews, Jason Agron
2012	—	`conf`	Developing application-specific multiprocessor platforms on FPGAs. ReConFig Sen Ma, Miaoqing Huang, David Andrews
2012	—	`conf`	Scalable Memory Hierarchies for Embedded Manycore Systems. ARC Sen Ma, Miaoqing Huang, Eugene Cartwright, David Andrews
2011	J	`jnl`	A Streaming High-Throughput Linear Sorter System with Contention Buffering. Int. J. Reconfigurable Comput. Jorge L. Ortiz, David Andrews
2011	—	`conf`	Creating HW/SW co-designed MPSoPC's from high level programming models. HPCS Eugene Cartwright, Sen Ma, David Andrews, Miaoqing Huang
2010	—	`conf`	A configurable high-throughput linear sorter system. IPDPS Workshops Jorge L. Ortiz, David Andrews
2010	—	`conf`	Configurable Processor Architectures: History and Trends. ERSA David Andrews, Christian Plessl
2010	Misc	`conf`	Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive. FCCM Jason Agron, David Andrews
2010	—	`conf`	Modular design of fully pipelined accumulators. FPT Miaoqing Huang, David Andrews
2010	—	`conf`	Operating System Structures for Multiprocessor Systems on Programmable Chip. ReConFig Miaoqing Huang, David Andrews, Jason Agron
2010	—	`ed.`	Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA ERSA Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt
2009	B	`conf`	Building heterogeneous reconfigurable systems using threads. FPL Jason Agron, David Andrews
2009	Misc	`conf`	Building heterogeneous reconfigurable systems with a hardware microkernel. CODES+ISSS Jason Agron, David Andrews
2009	—	`conf`	Hardware Microkernels for Heterogeneous Manycore Systems. ICPP Workshops Jason Agron, David Andrews
2008	J	`jnl`	Achieving Programming Model Abstractions for Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. David Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp
2008	C	`conf`	An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications. ISORC Elias Teodoro Silva Jr., David Andrews, Carlos Eduardo Pereira, Flávio Rech Wagner
2008	—	`conf`	Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. ARC Shane Santner, Wesley Peck, Jason Agron, David Andrews
2007	B	`conf`	Supporting High Level Language Semantics Within Hardware Resident Threads. FPL Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David Andrews
2006	Misc	`conf`	Enabling a Uniform Programming Model Across the Software/Hardware Boundary. FCCM Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews
2006	B	`conf`	Hthreads: A Computational Model for Reconfigurable Devices. FPL Wesley Peck, Erik K. Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David Andrews
2006	A	`conf`	Run-Time Services for Hybrid CPU/FPGA Systems on Chip. RTSS Jason Agron, Wesley Peck, Erik K. Anderson, David Andrews, Ed Komp, Ron Sass, Fabrice Baijot, Jim Stevens
2005	A	`conf`	Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms. IPDPS Razali Jidin, David Andrews, Wesley Peck, Dan Chirpich, Kevin Stout, John M. Gauch
2004	J	`jnl`	Programming Models for Hybrid CPU/FPGA Chips. Computer David Andrews, Douglas Niehaus, Peter J. Ashenden
2004	J	`jnl`	Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link. IEEE Micro David Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden
2003	A	`conf`	Architectural Frameworks for MPP Systems on a Chip. IPDPS David Andrews, Douglas Niehaus
2003	A	`conf`	SCIMPS: An Integrated Approach to Distributed Processing in Sensor Webs. IPDPS David Andrews, Joe Evans, Venumadhav Mangipudi, Aditya Mandapaka
2003	—	`conf`	Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation. WORDS Fall Douglas Niehaus, David Andrews
2002	A	`conf`	A Framework for Using Benefit Functions In Complex Real Time Systems. IPDPS David Andrews, Lonnie R. Welch, David M. Chelberg, Scott A. Brandt
2002	J	`jnl`	Interprocess communications in the AN/BSY-2 distributed computer system: a case study. J. Syst. Softw. David Andrews, Paul Austin, Peter Costello, David O. LeVan