Darío Suárez Gracia

47 papers A* 3A 3C 4Misc 3Journal 25Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores. IEEE Trans. Circuits Syst. Artif. Intell. Samuel Pérez Pedrajas, Javier Resano, Darío Suárez Gracia
2025	A*	`conf`	A. Delegato: Locality-Aware Atomic Memory Operations on Chiplets. MICRO Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Miquel Moretó
2025	C	`conf`	FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems. DSD Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Didier Martinot, Arnaud Grasset, Miquel Moretó
2025	Misc	`conf`	Tuple Spaces for Workflow Scheduling and Core-Level Malleability in Hpc. HiPC Juan Asensio Ayesa, Darío Suárez Gracia, Lluís Castrillo-Acuña
2024	A	`conf`	SpectralWaste Dataset: Multimodal Data for Waste Sorting Automation. IROS Sara Casao, Fernando Peña, Alberto Sabater, Rosa Castillón, Darío Suárez Gracia, Eduardo Montijano, Ana C. Murillo
2024	J	`jnl`	SpectralWaste Dataset: Multimodal Data for Waste Sorting Automation. CoRR Sara Casao, Fernando Peña, Alberto Sabater, Rosa Castillón, Darío Suárez Gracia, Eduardo Montijano, Ana C. Murillo
2023	A*	`conf`	DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. ISCA Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Alejandro Rico, Miquel Moretó
2022	J	`jnl`	A cross-platform OpenVX library for FPGA accelerators. J. Syst. Archit. Maria Angélica Dávila-Guzmán, Lester Kalms, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Diana Göhringer
2022	—	`conf`	Efficient Semantic Segmentation with Hyperspectral Images. ROBOT (1) Fernando Peña, Pilar Vidal Aguilar, Darío Suárez Gracia, Ana C. Murillo
2022	J	`jnl`	Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo
2022	—	`conf`	peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals
2021	C	`conf`	A Cross-Platform OpenVX Library for FPGA Accelerators. PDP Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Lester Kalms, Diana Göhringer
2021	J	`jnl`	A learning experience toward the understanding of abstraction-level interactions in parallel applications. J. Parallel Distributed Comput. Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez
2021	J	`jnl`	Analytical Model for Memory-Centric High Level Synthesis-Generated Applications. IEEE Trans. Computers Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2021	J	`jnl`	On the use of many-core Marvell ThunderX2 processor for HPC workloads. J. Supercomput. Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Miquel Moretó
2021	J	`jnl`	RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU. CoRR Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia
2020	Misc	`conf`	An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. FCCM Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2020	J	`jnl`	Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis. CoRR Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2020	J	`jnl`	DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files. IEEE Access Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero
2020	J	`jnl`	Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J. Supercomput. Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez
2019	J	`jnl`	A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distributed Comput. Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera
2019	J	`jnl`	An Aging-Aware GPU Register File Design Based on Data Redundancy. IEEE Trans. Computers Alejandro Valero, Francisco Candel, Darío Suárez Gracia, Salvador Petit, Julio Sahuquillo
2019	J	`jnl`	Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL. J. Supercomput. Maria Angelica Davila Guzman, Raúl Nozal, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, José Luis Bosque
2019	J	`jnl`	Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
2019	J	`jnl`	Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. J. Syst. Archit. Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez
2019	—	`conf`	Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
2019	J	`jnl`	Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
2018	J	`jnl`	AISC: Approximate Instruction Set Computer. CoRR Alexandra Ferreron, Jesús Alastruey-Benedé, Darío Suárez Gracia, Ulya R. Karpuzcu
2018	J	`jnl`	Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2018	—	`conf`	Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems. HPCS Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2017	—	`conf`	Abstract Representation of Shared Data for Heterogeneous Computing. LCPC Tushar Kumar, Aravind Natarajan, Wenjia Ruan, Mario Badr, Darío Suárez Gracia, Calin Cascaval
2017	C	`conf`	Exploiting Data Compression to Mitigate Aging in GPU Register Files. SBAC-PAD Francisco Candel, Alejandro Valero, Salvador Petit, Darío Suárez Gracia, Julio Sahuquillo
2017	—	`conf`	Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2016	J	`jnl`	Analysis of network-on-chip topologies for cost-efficient chip multiprocessors. Microprocess. Microsystems Marta Ortín-Obón, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals Yúfera
2016	J	`jnl`	Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. IEEE Trans. Computers Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Pablo Ibáñez
2016	J	`jnl`	Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs. J. Parallel Distributed Comput. Marta Ortín-Obón, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
2015	J	`jnl`	Concurrency in Mobile Browser Engines. IEEE Pervasive Comput. Calin Cascaval, Pablo Montesinos-Ortego, Behnam Robatmili, Darío Suárez Gracia
2014	C	`conf`	Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals
2014	A	`conf`	Dynamic construction of circuits for reactive traffic in homogeneous CMPs. DATE Marta Ortín, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
2014	J	`jnl`	Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM Trans. Archit. Code Optim. Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera
2013	—	`conf`	Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. INA-OCMC@HiPEAC Marta Ortín, Alexandra Ferreron, Jorge Albericio, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
2013	—	`conf`	Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. ARCS Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera
2012	—	`conf`	Automatic discovery of performance and energy pitfalls in HTML and CSS. IISWC Adrian Sampson, Calin Cascaval, Luis Ceze, Pablo Montesinos, Darío Suárez Gracia
2012	J	`jnl`	LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera
2009	A	`conf`	Light NUCA: A proposal for bridging the inter-cache latency gap. DATE Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals
2009	A*	`conf`	SigRace: signature-based data race detection. ISCA Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas
2007	Misc	`conf`	A proposal to introduce power and energy notions in computer architecture laboratories. WCAE Alicia Asín Pérez, Darío Suárez Gracia, Víctor Viñals Yúfera