Darshana Jayasinghe

25 papers A* 2A 2B 3C 1Misc 2Journal 11Unranked 4
YearRankTypeTitle / Venue / Authors
2025 A* conf
A Novel Covert Timing Channel for Cloud FPGAs.
DAC
Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
2025 J jnl
Approximate Multiplier Induced Error Propagation in Deep Neural Networks.
CoRR
A. M. H. H. Alahakoon, Hassaan Saadat, Darshana Jayasinghe, Sri Parameswaran
2025 A conf
JitFilt: Mitigate Jitter-based Side Channel Analysis Attacks.
ICCAD
Darshana Jayasinghe, Yuanhua Zhong, Sri Parameswaran
2024 J jnl
1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Darshana Jayasinghe, Brian Udugama, Sri Parameswaran
2024 J jnl
Physical and Software Based Fault Injection Attacks Against TEEs in Mobile Devices: A Systemisation of Knowledge.
CoRR
Aaron Joy, Ben Soh, Zhi Zhang, Sri Parameswaran, Darshana Jayasinghe
2024 B conf
Sensors for Remote Power Attacks: New Developments and Challenges.
ASPDAC
Brian Udugama, Darshana Jayasinghe, Sri Parameswaran
2023 — conf
FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers.
ASP-DAC
Darshana Jayasinghe, Brian Udugama, Sri Parameswaran
2022 J jnl
A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
2022 J jnl
VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
2021 J jnl
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks.
ACM Trans. Design Autom. Electr. Syst.
Darshana Jayasinghe, Aleksandar Ignjatovic, Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran
2021 J jnl
UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks.
IEEE Access
Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2020 B conf
LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs.
FPL
Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran
2019 A* conf
RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks.
DAC
Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2019 A conf
SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks.
ICCAD
Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2017 Misc conf
NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks.
VLSID
Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2016 — conf
Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure.
Conf. Computing Frontiers
Darshana Jayasinghe, Shivam Bhasin, Sri Parameswaran, Aleksandar Ignjatovic
2016 — conf
Template Attacks with Partial Profiles and Dirichlet Priors: Application to Timing Attacks.
HASP@ISCA
Eloi de Chérisey, Sylvain Guilley, Olivier Rioul, Darshana Jayasinghe
2015 Misc conf
QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks.
CASES
Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2015 — conf
Side channel attacks in embedded systems: A tale of hostilities and deterrence.
ISQED
Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran
2014 J jnl
Accelerating Correlation Power Analysis Using Graphics Processing Units.
CoRR
Hasindu Gamaarachchi, Roshan G. Ragel, Darshana Jayasinghe
2014 C conf
Advanced modes in AES: Are they safe from power analysis based side channel attacks?
ICCD
Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
2014 J jnl
Constant time encryption as a countermeasure against remote cache timing attacks.
CoRR
Darshana Jayasinghe, Roshan G. Ragel, Dhammika Elkaduwe
2014 J jnl
Countermeasures against Bernstein's remote cache timing attack.
CoRR
Janaka Alawatugoda, Darshana Jayasinghe, Roshan G. Ragel
2013 J jnl
Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.
IET Circuits Devices Syst.
Jude Angelo Ambrose, Héctor Pettenghi, Darshana Jayasinghe, Leonel Sousa
2011 B conf
A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks.
TrustCom
Ankita Arora, Sri Parameswaran, Roshan G. Ragel, Darshana Jayasinghe