Darsen D. Lu - RankMe

11 papers Journal 7Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Quantum-Chiplet: A VLSI-Like Methodology for Hierarchical Quantum Design and Verification. ISVLSI Hao-Yu Lu, Yu-Ting Kao, Yeong-Jar Chang, Jason Gemsun Young, Darsen D. Lu
2024	J	`jnl`	A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Fang-Yi Gu, Cheng-Han Yang, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu, Ulf Schlichtmann
2024	J	`jnl`	Numerical Simulations of Gate-Granularity- Induced Subthreshold Characteristics Deterioration of MOSFETs Magnified at Cryogenic Temperatures. IEEE Access Kuo-Hsing Kao, Zong-Hong Wang, Yu-Chia Pai, Chen-Chi Cheng, Darsen D. Lu, Wen-Jay Lee, Nan-Yow Chen
2023	J	`jnl`	CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials. CoRR Hoang-Hiep Le, Md. Aftab Baig, Wei-Chen Hong, Cheng-Hsien Tsai, Cheng-Jui Yeh, Fu-Xiang Liang, I-Ting Huang, Wei-Tzu Tsai, Ting-Yin Cheng, Sourav De, Nan-Yow Chen, Wen-Jay Lee, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu
2023	—	`conf`	MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. ESSDERC W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu
2022	—	`conf`	First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. VLSI Technology and Circuits X.-R. Yu, Wen Hsin Chang, T.-C. Hong, P.-J. Sung, A. Agarwal, G.-L. Luo, C.-T. Wu, K.-H. Kao, C.-J. Su, Shu-Wei Chang, W.-H. Lu, P.-Y. Fu, J.-H. Lin, P.-H. Wu, T.-C. Cho, William Cheng-Yu Ma, Darsen D. Lu, T.-S. Chao, Tatsuro Maeda, Yao-Jen Lee, W.-F. Wu, W.-K. Yeh, Yeong-Her Wang
2021	J	`jnl`	Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network. CoRR Sourav De, Yao-Jen Lee, Darsen D. Lu
2021	J	`jnl`	Neuromorphic Computing with Deeply Scaled Ferroelectric FinFET in Presence of Process Variation, Device Aging and Flicker Noise. CoRR Sourav De, Bo-Han Qiu, Wei-Xuan Bu, Md. Aftab Baig, Chung-Jun Su, Yao-Jen Lee, Darsen D. Lu
2020	J	`jnl`	Compact Device Models for FinFET and Beyond. CoRR Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang
2020	—	`conf`	Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K. DRC Sourav De, Md. Aftab Baig, Bo-Han Qiu, Darsen D. Lu, Po-Jung Sung, Fu. K. Hsueh, Yao-Jen Lee, Chun-Jung Su
2010	J	`jnl`	Compact Modeling of Variation in FinFET SRAM Cells. IEEE Des. Test Comput. Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu