Darren Anand - RankMe

13 papers A 1Misc 1Journal 5Unranked 6

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory. NATW Eric Hunt-Schroeder, Darren Anand, Edward Hwang, Aaron Cummings, Matthew Deming, Michael Roberge, Michael Ziegerhofer
2018	—	`conf`	14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. VLSI Circuits Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata
2011	J	`jnl`	Embedded DRAM in 45-nm Technology and Beyond. IEEE Des. Test Comput. Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli
2010	—	`conf`	A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. CICC Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
2007	—	`conf`	A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
2006	—	`conf`	Low Cost Test of High Bandwidth Embedded Memories. CICC Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin
2005	J	`jnl`	A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva
2004	Misc	`conf`	Generating At-Speed Array Fail Maps with Low-Speed ATE. VTS Michael R. Nelms, Kevin W. Gorman, Darren Anand
2003	J	`jnl`	A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier
2003	J	`jnl`	An On-Chip Self-Repair Calculation and Fusing Methodology. IEEE Des. Test Comput. Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater
2002	J	`jnl`	Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. IBM J. Res. Dev. John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek
2001	A	`conf`	Embedded DRAM built in self test and methodology for test insertion. ITC Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek
2001	—	`conf`	Shared fuse macro for multiple embedded memory devices with redundancy. CICC Michael R. Ouellette, Darren Anand, Peter Jakobsen