Dariusz Kania - RankMe

41 papers A 1C 4Journal 26Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Automatic Key Detection in Audio Recordings Using the Signature of Fifths. IEEE Access Tomasz Lukaszewicz, Dariusz Kania
2025	J	`jnl`	SOP Network Optimization Methods Aimed at Reducing Switching Activity. IEEE Access Bernard Wyrwol, Marcin Kubica, Dariusz Kania
2025	J	`jnl`	Trajectory of Fifths Based on Chroma Subbands Extraction-A New Approach to Music Representation, Analysis, and Classification. IEEE Trans. Pattern Anal. Mach. Intell. Tomasz Lukaszewicz, Dariusz Kania
2025	J	`jnl`	Trajectory of Fifths in Tonal Mode Detection. IEEE Access Tomasz Lukaszewicz, Dariusz Kania
2024	J	`jnl`	Switching Activity Reduction of SOP Networks. IEEE Access Marcin Kubica, Boleslaw Pochopien, Dariusz Kania
2023	J	`jnl`	Decomposition Approaches for Power Reduction. IEEE Access Adam Opara, Marcin Kubica, Dariusz Kania
2022	J	`jnl`	A Music Classification Approach Based on the Trajectory of Fifths. IEEE Access Tomasz Lukaszewicz, Dariusz Kania
2021	J	`jnl`	Frequency Estimation in Interpolated Discrete Fourier Transform With Generalized Maximum Sidelobe Decay Windows for the Control of Power. IEEE Trans. Ind. Informatics Józef Borkowski, Janusz Mroczka, Adam Matusiak, Dariusz Kania
2021	—	`book`	Technology Mapping for LUT-Based FPGA Marcin Kubica, Adam Opara, Dariusz Kania
2021	J	`jnl`	Trajectory of Fifths in Music Data Mining. IEEE Access Dariusz Kania, Paulina Kania, Tomasz Lukaszewicz
2019	J	`jnl`	A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs. IEEE Access Marcin Kubica, Dariusz Kania, Józef Kulisz
2019	J	`jnl`	IEEE Access Special Section: Cyber-Physical Systems. IEEE Access Remigiusz Wisniewski, Grzegorz Benysek, Luís Gomes, Dariusz Kania, Theodore E. Simos, MengChu Zhou
2019	J	`jnl`	Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis. IEEE Access Adam Opara, Marcin Kubica, Dariusz Kania
2019	J	`jnl`	Postural Symmetry Evaluation Based on the Analysis of Temporary and Average CoP Displacements Registered During the Follow-Up Posturography. IEEE Access Tomasz Lukaszewicz, Dariusz Kania, Zenon Kidon, Krystyna Pethe-Kania
2019	—	`conf`	Simulation Comparison of Frequency Estimation Methods Applied for Power Control in Renewable Energy Systems. SMACD Józef Borkowski, Dariusz Kania
2018	—	`conf`	Influence of Noise on Multifrequency Signals for the Amplitude and Phase Estimation in Photovoltaic Systems with a DSP Processor. TSP Dariusz Kania, Jozef Borkowski, Janusz Mroczka
2018	J	`jnl`	Low Power Synthesis of Finite State Machines - State Assignment Decomposition Algorithm. J. Circuits Syst. Comput. Krzysztof Kajstura, Dariusz Kania
2018	J	`jnl`	Strategy of logic synthesis using MTBDD dedicated to FPGA. Integr. Adam Opara, Marcin Kubica, Dariusz Kania
2017	J	`jnl`	Area-oriented technology mapping for LUT-based logic blocks. Int. J. Appl. Math. Comput. Sci. Marcin Kubica, Dariusz Kania
2017	—	`conf`	Estimation methods of multifrequency signals with noise and harmonics for PV systems with a DSP processor. TSP Dariusz Kania, Jozef Borkowski
2017	J	`jnl`	Logic synthesis for FPGAs based on cutting of BDD. Microprocess. Microsystems Marcin Kubica, Adam Opara, Dariusz Kania
2016	J	`jnl`	Interpolated-DFT-Based Fast and Accurate Amplitude and Phase Estimation for the Control of Power. CoRR Jozef Borkowski, Dariusz Kania
2016	J	`jnl`	State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers. ACM Trans. Design Autom. Electr. Syst. Robert Czerwinski, Dariusz Kania
2015	J	`jnl`	Logic Decomposition for PAL-Based CPLDs. J. Circuits Syst. Comput. Dariusz Kania
2014	J	`jnl`	Interpolated-DFT-Based Fast and Accurate Frequency Estimation for the Control of Power. IEEE Trans. Ind. Electron. Jozef Borkowski, Dariusz Kania, Janusz Mroczka
2012	J	`jnl`	Area and speed oriented synthesis of FSMs for PAL-based CPLDs. Microprocess. Microsystems Robert Czerwinski, Dariusz Kania
2010	J	`jnl`	Decomposition-based logic synthesis for PAL-based CPLDs. Int. J. Appl. Math. Comput. Sci. Adam Opara, Dariusz Kania
2010	J	`jnl`	Logic synthesis based on decomposition for CPLDs. Microprocess. Microsystems Dariusz Kania, Adam Milik
2009	C	`conf`	CPLD-oriented Synthesis of Finite State Machines. DSD Robert Czerwinski, Dariusz Kania
2009	—	`conf`	State assignment and logic optimization for finite state machines. PDeS Robert Czerwinski, Dariusz Kania
2009	J	`jnl`	Synthesis of finite state machines for CPLDs. Int. J. Appl. Math. Comput. Sci. Robert Czerwinski, Dariusz Kania
2007	—	`conf`	A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. ACM Great Lakes Symposium on VLSI Dariusz Kania
2007	J	`jnl`	Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. J. Syst. Softw. Dariusz Kania, Józef Kulisz
2005	C	`conf`	A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD Dariusz Kania, Józef Kulisz, Adam Milik
2005	C	`conf`	Decomposition of Multi-Output Functions for CPLDs. DSD Dariusz Kania, Adam Milik, Józef Kulisz
2005	C	`conf`	State Assignment for PAL-based CPLDs. DSD Robert Czerwinski, Dariusz Kania
2002	A	`conf`	Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. DATE Dariusz Kania
2002	—	`conf`	Logic synthesis of multi-output functions for PAL-based CPLDs. FPT Dariusz Kania
2000	—	`conf`	A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs. EUROMICRO Dariusz Kania
2000	—	`conf`	Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. EUROMICRO Dariusz Kania
1999	—	`conf`	Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. EUROMICRO Dariusz Kania